source0.uc

来自「Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与」· UC 代码 · 共 21 行

;Reference Instructions
;TA
;sram (about sig_done & br_!signal[sram])
;(Microengine 0  run source0.uc
; Microengine 1  run source1.uc
; Microengine 2  run source2.uc
; Microengine 3  run source3.uc)
immed[$xfer0,0x10]
immed[base,0]
;To perform SRAM[0]:=3
sram[write, $xfer0, base, 0, 1], sig_done;Not Ask for SRAM completion signal , swap out this thread and it not waiting for any signal and just being READY.
wait#:
br_!signal[sram, wait#], guess_branch,defer[1];the signal occuring 
nop
self#:
br[self#]
//(GUI: Memory Watch , Tread Status)
//demo(1): watch Microengine 0 's FIRST thead Execution. br!=signal[sram] polling SRAM signal event 
//demo(2): watch Microengine 1 four threads Execution. Context READY depending on SRAM signal event
//demo(3): watch Microengine 2 four threads Execution. Context READY depending on SRAM signal event 
//demo(4): watch Microengine 3 four threads Execution. Context READY NOT depending on SRAM signal event