source2.uc

来自「Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与」· UC 代码 · 共 17 行

;Reference Instructions
;TA
;sram (about ctx_swap)
;(Microengine 0  run source0.uc
; Microengine 1  run source1.uc
; Microengine 2  run source2.uc
; Microengine 3  run source3.uc)
immed[$xfer2,0x12]
;To perform SRAM[2]:=2
sram[write, $xfer2, base, 2, 1], ctx_swap,defer[1]; Ask for SRAM completion signal and swap out this thread causing it waiting for the signal. Using with defer[1].
immed[base,0]
self#:
br[self#]
//demo(1): watch Microengine 0 's FIRST thead Execution. br!=signal[sram] polling SRAM signal event 
//demo(2): watch Microengine 1 four threads Execution. Context READY depending on SRAM signal event
//demo(3): watch Microengine 2 four threads Execution. Context READY depending on SRAM signal event 
//demo(4): watch Microengine 3 four threads Execution. Context READY NOT depending on SRAM signal event