source1.uc

来自「Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与」· UC 代码 · 共 23 行

;Reference Instructions
;TA
;sram (about SRAM Queue)
;(The first Hardware Tread of 6 Microengines execute this code at the same time .)
.xfer_order $xfer0 $xfer1
immed[$xfer0,0]
immed[$xfer1,1]
immed[$xfer2,1]
immed[base,0]
sram[write, $xfer0, base, 0, 2], priority;sram[base+0] := $xfer0 , sram[base+1] := $xfer1 
sram[write, $xfer2, base, 2, 1];sram[base+2] := $xfer2 , default Write/Order Queue
self#:
br[self#]
//
//demo(1) - (GUI: History->Queues ,Queue Status) 
//back-pressure(watching SRAM Priority Queue) : back-pressure emerged when Priority Queue reaches its threshold (Queue_Size - 6 = 8 - 6 =2)
//
//demo(2) - (GUI: History->Queues ,Queue Status) 
//SRAM Command Service Priority : After Priority Queue is drained , then instructions in Write/Order Queue begin to execute.
//
//demo(3)
//Understand : SRAM command time differentiation. FOR the consideration of Performance and Realtime property.