demo6.dwp

Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与Demo Code.

# IXP1200 Developer Workbench Project File
# Format Version 7.00
#********  Do not edit this file ***********

# Begin Project demo6
CHIP_TYPE= 1
MIN_REVISION_NUM= 0
MAX_REVISION_NUM= -1

# Begin Group Source Files

# Begin Source File
PATH = .\Source6.uc
# End Source File
# End Group Source Files

# Begin Group Script Files
# End Group Script Files

# Begin Debug Startup Options
DO_MODEL_INIT = TRUE
ENABLE_STRONGARM = FALSE
ENABLE_PCI_INTERFACE = FALSE
TAG_SDRAM = FALSE
TAG_SRAM = FALSE
TAG_FLASH_MEMORY = FALSE
SIM_STEP_UNIT = Core
# End Debug Startup Options

# Begin Clock Frequencies
USE_STANDARD_FREQ = TRUE
STANDARD_FREQ_INDEX = 16
CUSTOM_CLK_FREQ = 166
IX_BUS_CLK_FREQ = 66
PCI_BUS_CLK_FREQ = 83

# End Clock Frequencies

# Begin Chip 
FBUS_NAME = 
RDYBUS_NAME = 

# Begin Chip Configuration Info

# Begin Ixbi Configuration Info
TEMPLATE_NAME = 
PROGRAM_VALID = FALSE
RDYBUS_TEMPLATE_CTL = 100
RCV_RDY_CTL = c0
XMIT_RDY_CTL = c0
FP_READY_WAIT = 0
RDYBUS_TEMPLATE_PROG1 = 0
RDYBUS_TEMPLATE_PROG2 = 0
RDYBUS_TEMPLATE_PROG3 = 0
RDYBUS_SYNCH_COUNT_DEFAULT = 0
# End Ixbi Configuration Info

# Begin Pci Configuration Info
TEMPLATE_NAME = 
INIT_CONFIG_SPACE = FALSE
PERFORM_CFI = FALSE
ENABLE_IO_SPACE = FALSE
ENABLE_MASTER = FALSE
ENABLE_MASTER_WRITE_INVALIDATE = FALSE
ENABLE_MEM_SPACE = FALSE
DRAM_WINDOW_SIZE = 0
MEMORY_WINDOW_SIZE = 0
DRAM_BASE_ADDR_EDIT = 0
IO_BASE_ADDR_EDIT = 0
MEM_BASE_ADDR_EDIT = 0
ENABLE_PCI_BUS_ARBITER = FALSE
ENABLE_PCI_CENTRAL_FUNCTION = FALSE
# End Pci Configuration Info

# Begin Sdram Configuration Info
TEMPLATE_NAME = 
SDRAM_CSR = 2
SDRAM_MEMINIT = 0
SDRAM_MEMCTL0 = 82c9
SDRAM_MEMCTL1 = 202141
SDRAM_UNITS = 32
# End Sdram Configuration Info

# Begin Sram Configuration Info
SRAM_CSR = 4800
SRAM_SLOWPORT_CONFIG = 313f0502
SRAM_SLOW_CONFIG = a2341
SRAM_BOOT_CONFIG = 1c200904
NUM_SRAM_BANKS = 2
NUM_BOOT_ROM_BANKS = 1
SLOW_PORT_TEMPLATE_NAME = 
BOOT_ROM_TEMPLATE_NAME = 
# End Sram Configuration Info
# End Chip Configuration Info

# Begin MicroEngine 0
# End MicroEngine

# Begin MicroEngine 1
# End MicroEngine

# Begin MicroEngine 2
# End MicroEngine

# Begin MicroEngine 3
# End MicroEngine

# Begin MicroEngine 4
# End MicroEngine

# Begin MicroEngine 5
# End MicroEngine
# End Chip

# Begin Assembler Settings
ROOT_FILE = .\Source6.uc
OPTIMIZE = FALSE
NEW_REGISTER_ALLOCATOR = FALSE
OUTPUT = .\Source6.list
EDIT_OVERRIDE = FALSE
# End Assembler Settings

# Begin Linker Settings
CHIP_NAME = 
OUTPUT = demo6
GEN_HEX_C_FILE = FALSE
# Begin Linker Map
MICROENGINE_NUMBER = 0
MICROENGINE_LIST_FILE = .\Source6.list
# End Linker Map
# End Linker Settings

# Begin Rsc-IXBus Configuration Info
RSC_USE_CONFIG = false
RSC_TEMPLATE_NAME = 
RSC_TEMPLATE_DESC = 
RSC_TEMPLATE_LINK = 
RSC_TEMPLATE_BMP_LINK = 
RSC_FOREIGN_MODEL_COMMAND = 
RSC_NUM_OF_IXP = 1
RSC_NUM_OF_RSC = 0
RSC_NUM_OF_IXBUS = 1
# End Rsc-IXBus Configuration Info
# End Project