source6.ucp

来自「Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与」· UCP 代码 · 共 51 行

.line 1 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc"
;Local Register instructions
;TA
;find bit set 
no_bit_set#:
immed_w1[gpr3,0xABC0]
immed_w1[gpr4,0x000A]
immed_w0[gpr4,0xBCDE]
; assume that all input gpr was 0 except:
; gpr3 = 0xABC00000 : for upper 16 bits, bit 6 is first set.
; gpr4 = 0x000ABCDE : for lower 16 bits, bit 10 is first set  when masking the lowest byte"DE".
;- find_bset instruction counter=0
find_bset[ gpr0 ], clr_results;clear both result registers ,and then test lower half of gpr0 
find_bset[ gpr0, >>16 ] ; test upper half of gpr0
find_bset[ gpr1 ]
find_bset[ gpr1, >>16 ]
find_bset[ gpr2 ]
find_bset[ gpr2, >>16 ]
find_bset[ gpr3 ]
find_bset[ gpr3, >>16 ] ;- find_bset instruction counter=7
immed[ mask_reg, 0xFF00 ] ; low byte is clear ==> don’t test it
; test lower half of gpr4 while masking out low byte
find_bset_with_mask[ mask_reg, gpr4 ]
find_bset[ gpr4, >>16 ] ;- find_bset instruction counter=8
find_bset[ gpr5 ]
find_bset[ gpr5, >>16 ]
find_bset[ gpr6 ]
find_bset[ gpr6, >>16 ]
find_bset[ gpr7 ]
find_bset[ gpr7, >>16 ];- find_bset instruction counter=15 
;Test up to 16 consecutive 16 bit fields
nop;required for 3 cycle latency
nop;required for 3 cycle latency
nop;required for 3 cycle latency
load_bset_result2[ temp2 ]
;load_bset_result set alu contional code
load_bset_result1[ temp1 ], clr_results ; read results ,and then clear both result registers
;load_bset_result set alu contional code
br=0[ no_bit_set# ]; branch if no bit was set
; else the results would be:
; temp1 = 0x176
; temp2 = 0x18A
; result register  Format :
; +++++++++++++++++++++++++++++++++++++++++++
; | reserved|locked|find_bset |first bit set| 
; |         |      |counter   |position     | 
; +++++++++++++++++++++++++++++++++++++++++++
;               8      4             4
self#:
br[self#]