📄 source6.uci
字号:
; LD_FIELD formats
LD_FIELD_B[,,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/LD_FIELD, REL_A_OP/@1, BYTE_MASK/@2, REL_B_OP/@3, :@4, LD_FIELD_OP_SWAP/FALSE"
LD_FIELD_A[,,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/LD_FIELD, REL_B_OP/@1, BYTE_MASK/@2, REL_A_OP/@3, :@4, LD_FIELD_OP_SWAP/TRUE"
LD_FIELD_W_CLR_B[,,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/LD_FIELD, REL_A_OP/@1, BYTE_MASK/@2, REL_B_OP/@3, :@4, LD_FIELD_OP_SWAP/FALSE,
LD_INTO_ZEROS/TRUE"
LD_FIELD_W_CLR_A[,,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/LD_FIELD, REL_B_OP/@1, BYTE_MASK/@2, REL_A_OP/@3, :@4, LD_FIELD_OP_SWAP/TRUE,
LD_INTO_ZEROS/TRUE"
; _B or _A refers to side that would contain the mask...not the field to be tested
FIND_BSET_A[,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/--, REL_B_OP/@1, :@2, LD_FIELD_OP_SWAP/FALSE"
FIND_BSET_B[,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@1, REL_B_OP/--, :@2, LD_FIELD_OP_SWAP/TRUE"
FIND_BSET_WITH_MASK_A[,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@1, REL_B_OP/@2, :@3, BSET_MASK/TRUE, LD_FIELD_OP_SWAP/FALSE"
FIND_BSET_WITH_MASK_B[,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@2, REL_B_OP/@1, :@3, BSET_MASK/TRUE, LD_FIELD_OP_SWAP/TRUE"
FIND_BSET_WITH_MASK_AI[,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@1, REL_B_OP/@2, :@3, IMMED_OP/TRUE, AB_IMMED/A,
BSET_MASK/TRUE, LD_FIELD_OP_SWAP/FALSE"
FIND_BSET_WITH_MASK_BI[,,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@2, REL_B_OP/@1, :@3, IMMED_OP/TRUE, AB_IMMED/B,
BSET_MASK/TRUE, LD_FIELD_OP_SWAP/TRUE"
; _B ==> result immediate data loaded on B side (destination is on A side)
LOAD_BSET_RESULT1_B[] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@1, REL_B_OP/--, IMMED_OP/TRUE, AB_IMMED/B,
BSET_RES1/TRUE, LD_FIELD_OP_SWAP/FALSE, <<0"
LOAD_BSET_RESULT1_A[] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/--, REL_B_OP/@1, IMMED_OP/TRUE, AB_IMMED/A,
BSET_RES1/TRUE, LD_FIELD_OP_SWAP/TRUE, <<0"
LOAD_BSET_RESULT2_B[] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/@1, REL_B_OP/--, IMMED_OP/TRUE, AB_IMMED/B,
BSET_RES2/TRUE, LD_FIELD_OP_SWAP/FALSE, <<0"
LOAD_BSET_RESULT2_A[] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/FIND_BSET, REL_A_OP/--, REL_B_OP/@1, IMMED_OP/TRUE, AB_IMMED/A,
BSET_RES2/TRUE, LD_FIELD_OP_SWAP/TRUE, <<0"
CLR_RESULTS "BSET_CLR_RESULT/TRUE"
LOCAL_CSR_RD[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/FBOX_CSR, FBOX_CSR_ADDRESS/@1, FBOX_CSR_OP/RD, FBOX_CSR_ZERO/FALSE"
LOCAL_CSR_WR[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/FBOX_CSR, FBOX_CSR_ADDRESS/@1, AB_REL_SRC/@2, FBOX_CSR_OP/WR, FBOX_CSR_ZERO/FALSE"
LOCAL_CSR_WR_Z[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/FBOX_CSR, FBOX_CSR_ADDRESS/@1, AB_REL_SRC/@2, FBOX_CSR_OP/WR, FBOX_CSR_ZERO/TRUE"
; reference issuing formats
SRAM[,,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD2/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5"
SRAM_AI[,,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD2/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, IMMED_OP/TRUE, AB_IMMED/A"
SRAM_BI[,,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD2/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, IMMED_OP/TRUE, AB_IMMED/B"
SCRATCH[,,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD2/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, SCRATCH_PAD/TRUE"
SCRATCH_AI[,,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD2/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, IMMED_OP/TRUE,
AB_IMMED/A, SCRATCH_PAD/TRUE"
SCRATCH_BI[,,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD2/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, IMMED_OP/TRUE,
AB_IMMED/B, SCRATCH_PAD/TRUE"
SDRAM[,,,,] "SDRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5"
SDRAM_AI[,,,,] "SDRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, IMMED_OP/TRUE, AB_IMMED/A"
SDRAM_BI[,,,,] "SDRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/@1, XFER_REG/@2, REL_A_OP/@3, REL_B_OP/@4, REF_CNT/@5, IMMED_OP/TRUE, AB_IMMED/B"
PCI_DMA[,,] "SDRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WRITE, XFER_REG/--, REL_A_OP/@1, REL_B_OP/@2, REF_CNT/@3, PRIORITY_QUEUE/PRIORITY, ORDER_QUEUE/ORDERED"
PCI_DMA_AI[,,] "SDRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WRITE, XFER_REG/--, REL_A_OP/@1, REL_B_OP/@2, REF_CNT/@3, PRIORITY_QUEUE/PRIORITY, ORDER_QUEUE/ORDERED, IMMED_OP/TRUE, AB_IMMED/A"
PCI_DMA_BI[,,] "SDRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WRITE, XFER_REG/--, REL_A_OP/@1, REL_B_OP/@2, REF_CNT/@3, PRIORITY_QUEUE/PRIORITY, ORDER_QUEUE/ORDERED, IMMED_OP/TRUE, AB_IMMED/B"
R_FIFO_RD[,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/RD_RFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4"
R_FIFO_RD_AI[,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/RD_RFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4, IMMED_OP/TRUE, AB_IMMED/A"
R_FIFO_RD_BI[,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/RD_RFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4, IMMED_OP/TRUE, AB_IMMED/B"
;R_FIFO_RD[,] "R_FIFO_RD UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/RD_RFIFO, XFER_REG/@1, REF_CNT/@2"
;R_FIFO_RD_AI[,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/RD_RFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@2, IMMED_OP/TRUE, AB_IMMED/A"
;R_FIFO_RD_BI[,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/RD_RFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@2, IMMED_OP/TRUE, AB_IMMED/B"
T_FIFO_WR[,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WR_TFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4"
T_FIFO_WR_AI[,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WR_TFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4, IMMED_OP/TRUE, AB_IMMED/A"
T_FIFO_WR_BI[,,,] "SRAM UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WR_TFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4, IMMED_OP/TRUE, AB_IMMED/B"
;T_FIFO_WR[,] "T_FIFO_WR UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WR_TFIFO, XFER_REG/@1, REF_CNT/@2"
;T_FIFO_WR_AI[,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WR_TFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4, IMMED_OP/TRUE, AB_IMMED/A"
;T_FIFO_WR_BI[,] "UW_TYPE/EXT_2_SRC, EXT_2_OP_CMD1/WR_TFIFO, XFER_REG/@1, REL_A_OP/@2, REL_B_OP/@3, REF_CNT/@4, IMMED_OP/TRUE, AB_IMMED/B"
CSR[,,,def] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/@1, XFER_REG/@2, CSR_ADDRESS/@3, REF_CNT/@4"
FAST_WR[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/FAST_WR, FAST_WR_DATA/@1, FAST_WR_ADDRESS/@2"
;HASH_LD_MULT_48[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_MULTIPLIER_48_LO,
; REF_CNT/WORD_CNT_2"
;HASH_LD_MULT_64[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_MULTIPLIER_64_LO,
; REF_CNT/WORD_CNT_2"
HASH1_48[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_48,
REF_CNT/WORD_CNT_2"
HASH2_48[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_48,
REF_CNT/WORD_CNT_4"
HASH3_48[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_48,
REF_CNT/WORD_CNT_6"
HASH1_64[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_64,
REF_CNT/WORD_CNT_2"
HASH2_64[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_64,
REF_CNT/WORD_CNT_4"
HASH3_64[] "CSR UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CSR, EXT_1_OP_CMD_QUAL/WRITE, XFER_REG/@1, CSR_ADDRESS/HASH_64,
REF_CNT/WORD_CNT_6"
INDIRECT_REF "INDIRECT_REF/TRUE"
CTX_SWAP "CTX_SWAP/SWAP, VOLUNTARY_SWAP/FALSE"
VOLUNTARY_SWAP "CTX_SWAP/SWAP, VOLUNTARY_SWAP/TRUE"
SIG_DONE "SIG_DONE/SIG_DONE"
CHAIN_REF "CHAIN_REF/TRUE"
ORDERED "ORDER_QUEUE/ORDERED"
OPTIMIZE_MEM "ORDER_QUEUE/UNORDERED"
PRIORITY "PRIORITY_QUEUE/PRIORITY, ORDER_QUEUE/UNORDERED"
NO_OPTION ""
NO_SIGNAL ""
LOAD_CC "LOAD_CC/TRUE"
; LOAD IMMEDIATE format
IMMED[,,def] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, IMMED_SHF/@3, LOAD_WORD/FALSE, LOAD_BYTE/FALSE, INVERT/FALSE"
IMMED_NEG[,,def] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, IMMED_SHF/@3, LOAD_WORD/FALSE, LOAD_BYTE/FALSE, INVERT/TRUE"
;IMMED_[,,def] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA/@2, IMMED_SHF/@3, LOAD_AMT/32, INVERT/FALSE, OP_SWAP/TRUE"
;IMMED_NEG_[,,def] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA/@2, IMMED_SHF/@3, LOAD_AMT/32, INVERT/TRUE, OP_SWAP/TRUE"
;0011 "IMMED16 IMMED_SHF/0"
;0110 "IMMED16 IMMED_SHF/<<rot8"
;1100 "IMMED16 IMMED_SHF/<<rot16"
;1001 "IMMED16 IMMED_SHF/<<rot24"
IMMED_W0[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, LOAD_WORD/TRUE, INVERT/FALSE, IMMED_SHF/<<0"
IMMED_W1[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, LOAD_WORD/TRUE, INVERT/FALSE, IMMED_SHF/<<16"
IMMED_B0[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, LOAD_BYTE/TRUE, INVERT/FALSE, IMMED_SHF/<<0"
IMMED_B1[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, LOAD_BYTE/TRUE, INVERT/FALSE, IMMED_SHF/<<8"
IMMED_B2[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, LOAD_BYTE/TRUE, INVERT/FALSE, IMMED_SHF/<<16"
IMMED_B3[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_DATA_16_BIT/@2, LOAD_BYTE/TRUE, INVERT/FALSE, IMMED_SHF/<<24"
; LOAD_ADDR format (form of load immediate)
LOAD_ADDR[,] "UW_TYPE/IMMED, ABS_DEST/@1, IMMED_ADDR_FIELD/@2, IMMED_SHF/0, INVERT/FALSE"
; BRANCHES
BR[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/UNCOND, BRANCH_FIELD/@1"
BR<0[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/LESZ, BRANCH_FIELD/@1"
BR<0_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/LESZ, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR<0__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/LESZ, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR<=0[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/LEQZ, BRANCH_FIELD/@1"
BR<=0_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/LEQZ, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR<=0__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/LEQZ, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR>0[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/GTRZ, BRANCH_FIELD/@1"
BR>0_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/GTRZ, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR>0__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/GTRZ, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR>=0[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/GEQZ, BRANCH_FIELD/@1"
BR>=0_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/GEQZ, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR>=0__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/GEQZ, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR=0[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/EQSZ, BRANCH_FIELD/@1"
BR=0_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/EQSZ, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR=0__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/EQSZ, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR!=0[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NEQZ, BRANCH_FIELD/@1"
BR!=0_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NEQZ, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR!=0__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NEQZ, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR=COUT[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/COUT, BRANCH_FIELD/@1"
BR=COUT_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/COUT, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR=COUT__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/COUT, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR!=COUT[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NOT_COUT, BRANCH_FIELD/@1"
BR!=COUT_[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NOT_COUT, BRANCH_FIELD/@1, BRANCH_PIPE/2"
BR!=COUT__[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NOT_COUT, BRANCH_FIELD/@1, BRANCH_PIPE/3"
BR_MEM_LOCK[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/MEMLOCK, BRANCH_FIELD/@1"
BR=CTX[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/CTX, BRANCH_FIELD/@2, BRANCH_CTX_MASK/@1"
BR!=CTX[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/NOT_CTX, BRANCH_FIELD/@2, BRANCH_CTX_MASK/@1"
BR_!SIGNAL[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/EXTENDED, EXT_BRANCH_TYPE/@1, BRANCH_FIELD/@2, BRANCH_PIPE/3"
BR_INP_STATE[,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH, BRANCH_TYPE/EXTENDED, EXT_BRANCH_TYPE/@1, BRANCH_FIELD/@2, BRANCH_PIPE/3"
DEFER[] "DEFER_BRANCH/@1"
DEFER[] "SRAM MEM_DEFER/@1"
DEFER[] "SRAM_AI MEM_DEFER/@1"
DEFER[] "SRAM_BI MEM_DEFER/@1"
DEFER[] "SDRAM MEM_DEFER/@1"
DEFER[] "SDRAM_AI MEM_DEFER/@1"
DEFER[] "SDRAM_BI MEM_DEFER/@1"
DEFER[] "SCRATCH MEM_DEFER/@1"
DEFER[] "SCRATCH_AI MEM_DEFER/@1"
DEFER[] "SCRATCH_BI MEM_DEFER/@1"
DEFER[] "CTX_ARB MEM_DEFER/@1"
DEFER[] "CSR MEM_DEFER/@1"
DEFER[] "R_FIFO_RD MEM_DEFER/@1"
DEFER[] "R_FIFO_RD_AI MEM_DEFER/@1"
DEFER[] "R_FIFO_RD_BI MEM_DEFER/@1"
DEFER[] "T_FIFO_WR MEM_DEFER/@1"
DEFER[] "T_FIFO_WR_AI MEM_DEFER/@1"
DEFER[] "T_FIFO_WR_BI MEM_DEFER/@1"
DEFER[] "HASH1_48 MEM_DEFER/@1"
DEFER[] "HASH2_48 MEM_DEFER/@1"
DEFER[] "HASH3_48 MEM_DEFER/@1"
DEFER[] "HASH1_64 MEM_DEFER/@1"
DEFER[] "HASH2_64 MEM_DEFER/@1"
DEFER[] "HASH3_64 MEM_DEFER/@1"
GUESS_BRANCH "GUESS_BRANCH/TAKEN"
GUESS_BRANCH_NOT_TAKEN "GUESS_BRANCH/NOT_TAKEN"
; BRANCH ON BIT format
BR_BSET[,,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH_BIT, AB_REL_SRC/@1, BBS_SHIFT/@2, BRANCH_FIELD/@3, BBS_BIT_VAL/1"
BR_BCLR[,,] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/BRANCH_BIT, AB_REL_SRC/@1, BBS_SHIFT/@2, BRANCH_FIELD/@3, BBS_BIT_VAL/0"
BR=BYTE[,,,] "UW_TYPE/BR_BYTE, AB_REL_SRC/@1, BYTE_SPEC/@2, BR_BYTE_IMMED/@3, BRANCH_FIELD/@4,
BR_BYTE_SENSE/EQL"
BR!=BYTE[,,,] "UW_TYPE/BR_BYTE, AB_REL_SRC/@1, BYTE_SPEC/@2, BR_BYTE_IMMED/@3, BRANCH_FIELD/@4,
BR_BYTE_SENSE/NEQ"
; ALU_BRANCH format
JUMP[,] "UW_TYPE/BR_ALU, BRANCH_FIELD/@2, ABS_DEST/@1"
RTN[] "UW_TYPE/BR_ALU, ZERO_BASE_FIELD/ZERO, ABS_DEST/@1"
; context management formats
CTX_ARB[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/CONTEXT, SIGNAL_EVENT/@1, CTX_SWAP/SWAP,
VOLUNTARY_SWAP/FALSE"
LD_USTORE_WR_ADDR[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/USTORE, USTORE_ADDR/TRUE, ABS_DEST/@1"
WR_USTORE[] "UW_TYPE/EXT_1_SRC, EXT_1_OP_CMD/USTORE, USTORE_ADDR/FALSE, ABS_DEST/@1"
TARGETS "DUMMY/DUMMY"
;
; Register Allocation:
; A-Bank, relative GPRs (06)
; 00 gpr4
; 01 gpr0
; 02 gpr2
; 03 gpr5
; 04 gpr7
; 05 temp2
; A-Bank, absolute GPRs (00)
; B-Bank, relative GPRs (05)
; 00 mask_reg
; 01 gpr1
; 02 gpr3
; 03 gpr6
; 04 temp1
; B-Bank, absolute GPRs (00)
;
;
; Static Uword Distribution:
;
; alu: 0 ( 0.00%)
; alu_shf: 0 ( 0.00%)
; dbl_shf: 0 ( 0.00%)
; ld_field: 0 ( 0.00%)
; sram: 0 ( 0.00%)
; scratch: 0 ( 0.00%)
; sdram: 0 ( 0.00%)
; pci_dma: 0 ( 0.00%)
; t_fifo_wr: 0 ( 0.00%)
; r_fifo_rd: 0 ( 0.00%)
; hash: 0 ( 0.00%)
; csr: 0 ( 0.00%)
; fast_wr: 0 ( 0.00%)
; branch: 2 ( 7.41%)
; br_bit: 0 ( 0.00%)
; br?=byte: 0 ( 0.00%)
; jump: 0 ( 0.00%)
; rtn: 0 ( 0.00%)
; ctx_arb: 0 ( 0.00%)
; load_addr: 0 ( 0.00%)
; find_bset: 16 (59.26%)
; load_bset_resultx: 2 ( 7.41%)
; immed: 4 (14.81%)
; local_csr_rd: 0 ( 0.00%)
; local_csr_wr: 0 ( 0.00%)
; nop: 3 (11.11%)
; alu: 0 (100.00%)
;
; total: 27
;
; Number of exposed branch latency bubbles: 3 (100.00%)
;
.PAGE "Microcode Listing"
.import_var __chip_id __chip_revision __uengine_id
.%line 4 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
;Local Register instructions
;TA
;find bit set
no_bit_set#:
.%line 5 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
immed_w1[gpr3,0xabc0]
.%line 6 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
immed_w1[gpr4,0x000a]
.%line 7 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
immed_w0[gpr4,0xbcde]
.%line 12 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
; assume that all input gpr was 0 except:
; gpr3 = 0xABC00000 : for upper 16 bits, bit 6 is first set.
; gpr4 = 0x000ABCDE : for lower 16 bits, bit 10 is first set when masking the lowest byte"DE".
;- find_bset instruction counter=0
find_bset_b[ gpr0 ,0 ], clr_results;clear both result registers ,and then test lower half of gpr0
.%line 13 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr0, >>16 ] ; test upper half of gpr0
.%line 14 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_a[ gpr1 ,0 ]
.%line 15 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_a[ gpr1, >>16 ]
.%line 16 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr2 ,0 ]
.%line 17 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr2, >>16 ]
.%line 18 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_a[ gpr3 ,0 ]
.%line 19 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_a[ gpr3, >>16 ] ;- find_bset instruction counter=7
.%line 20 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
immed[ mask_reg, 0xff00 ] ; low byte is clear ==> don’t test it
.%line 22 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
; test lower half of gpr4 while masking out low byte
find_bset_with_mask_b[ mask_reg, gpr4 ,0 ]
.%line 23 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr4, >>16 ] ;- find_bset instruction counter=8
.%line 24 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr5 ,0 ]
.%line 25 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr5, >>16 ]
.%line 26 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_a[ gpr6 ,0 ]
.%line 27 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_a[ gpr6, >>16 ]
.%line 28 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr7 ,0 ]
.%line 29 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
find_bset_b[ gpr7, >>16 ];- find_bset instruction counter=15
.%line 31 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
;Test up to 16 consecutive 16 bit fields
nop;required for 3 cycle latency
.%line 32 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
nop;required for 3 cycle latency
.%line 33 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
nop;required for 3 cycle latency
.%line 34 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
load_bset_result2_b[ temp2 ]
.%line 36 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
;load_bset_result set alu contional code
load_bset_result1_a[ temp1 ], clr_results ; read results ,and then clear both result registers
.%line 38 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
;load_bset_result set alu contional code
br=0_[ no_bit_set# ]; branch if no bit was set
.%line 48 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
; else the results would be:
; temp1 = 0x176
; temp2 = 0x18A
; result register Format :
; +++++++++++++++++++++++++++++++++++++++++++
; | reserved|locked|find_bset |first bit set|
; | | |counter |position |
; +++++++++++++++++++++++++++++++++++++++++++
; 8 4 4
self#:
.%line 49 "D:\yxp\ixp1200\讲座\Intel IXP1200开发指南\开发指南2之demo工程\开发指南(2)之demo工程\demo6\Source6.uc" 1
br[self#]
; THE FOLLOWING WARNING MESSAGES WERE GENERATED BY THE PRE-PROCESSOR
; WARNING: GPR, "gpr0", was referenced, but never assigned to.
; WARNING: GPR, "gpr1", was referenced, but never assigned to.
; WARNING: GPR, "gpr2", was referenced, but never assigned to.
; WARNING: GPR, "gpr5", was referenced, but never assigned to.
; WARNING: GPR, "gpr6", was referenced, but never assigned to.
; WARNING: GPR, "gpr7", was referenced, but never assigned to.
; WARNING: GPR, "temp1", was assigned to but never referenced.
; WARNING: GPR, "temp2", was assigned to but never referenced.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -