source5.uci

Intel IXP1200开发指南. 包含IXP1200网络处理器PPT演示与Demo Code.

;    4 =		1
;    8 =		2
;    12 =	3
;    16 =	4
;    20 =	5
;    24 =	6
;    28 =	7
;	<<4 =   1
;	<<8 =	2
;	<<12 =	3
;	<<16 =	4
;	<<20 =	5
;	<<24 =	6
;	<<28 =	7

;.toc "   IMMED_LD_FIELD:  specifies immediate data for load_field uword"
;IMMED_LD_FIELD/=<19:12>,.default=<IMMED_LD_FIELD/0>,.validity=<.GTR[.TIME1, 0]>
;    0 =		0
;	@UINT

;.toc "   LD_FIELD_ROTATE:  specifies rotate/shift load_field uword"
;LD_FIELD_ROTATE/=<23>,.default=<LD_FIELD_ROTATE/SHIFT>,.validity=<.GTR[.TIME1, 0]>
;    SHIFT   = 0
;    ROTATE  = 1


;.toc "   LD_FIELD_SHIFT_CNTL:  specifies left rotate, or left/right shift or double shift"
;LD_FIELD_SHIFT_CNTL/=<23,17>,.default=<LD_FIELD_SHIFT_CNTL/LEFT_ROT>,.validity=<.GTR[.TIME1, 0]>
;    LEFT_ROT =    0
;    RIGHT =       1
;    LEFT =        2
;    DBL_SHF =     3

.toc "   LOAD_CC:  specifies whether to load new condition codes"
LOAD_CC/=<5>,.default=<LOAD_CC/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =   0
    TRUE =    1

.toc "   LD_FIELD_OPERAND_SWAP:  specifies A-B operand swap"
LD_FIELD_OP_SWAP/=<25>,.default=<LD_FIELD_OP_SWAP/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =     0
    TRUE =		1

LD_INTO_ZEROS/=<26>,.default=<LD_INTO_ZEROS/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =     0
    TRUE =		1



;------------- FIELDS SPECIFIC TO FIND_BSET FORMAT -------------

.toc "   BSET_MASK:  specifies a mask operand for find_bset"
BSET_MASK/=<24>,.default=<BSET_MASK/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =     0
    TRUE =		1

.toc "   BSET_RES1:  specifies a load of result1 register corresponding to find_bset"
BSET_RES1/=<22>,.default=<BSET_RES1/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =     0
    TRUE =		1

.toc "   BSET_RES2:  specifies a load of result2 register corresponding to find_bset"
BSET_RES2/=<21>,.default=<BSET_RES2/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =     0
    TRUE =		1

.toc "   BSET_CLR_RESULT:  specifies that result regs should be cleared"
BSET_CLR_RESULT/=<26>,.default=<BSET_CLR_RESULT/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =     0
    TRUE =		1
;------------- FIELDS SPECIFIC TO IMMEDIATE DATA FORMAT -------------


.toc "   IMMED_DATA_16_BIT:  specifies immediate data"
IMMED_DATA_16_BIT/=<5:0,16:7>,.default=<IMMED_DATA_16_BIT/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
    _DEFAULT_VALUE_ =    0
    @UINT_OR_INV

.toc "   IMMED_SHF:  specifies immediate data left shift amt"
IMMED_SHF/=<18:17>,.default=<IMMED_SHF/0>,.validity=<.GTR[.TIME1, 0]>
    0        = 0
    <<0      = 0
    <<00     = 0
    <<8      = 3
    <<08     = 3
    <<16     = 2
    <<24     = 1

.toc "   INVERT:  specifies whether to invert data before loading it"
INVERT/=<6>,.default=<INVERT/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE      = 0
    TRUE       = 1

.toc "   LOAD_WORD:  specifies loading 16 bits of immed data"
LOAD_WORD/=<20>,.default=<LOAD_WORD/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE      = 0
    TRUE       = 1


.toc "   LOAD_BYTE:  specifies loading a byte immed data"
LOAD_BYTE/=<19>,.default=<LOAD_BYTE/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE      = 0
    TRUE       = 1


; branch target automatically filled in by compiler
.toc "   IMMED_ADDR_FIELD"
IMMED_ADDR_FIELD/=<5:0,16:7>,.address,.validity=<.GTR[.TIME1, 0]>





;------------- FIELDS SPECIFIC TO MEM FORMAT -------------

.toc "   CMD QUAL FOR 2 OPERAND EXT OPCODE:  "
EXT_2_OP_CMD1/=<3:0>,.default=<EXT_2_OP_CMD1/READ>,.validity=<.GTR[.TIME1, 0]>
    READ =                0
    WRITE =               1
    T_FIFO_WR =           2
    R_FIFO_RD =           3
	FIND_BSET =			  4
    WR_TFIFO =            5
    RD_RFIFO =            6
    LD_FIELD =            7

.toc "   CMD QUAL FOR 2 OPERAND EXT OPCODE:  "
EXT_2_OP_CMD2/=<3:0>,.default=<EXT_2_OP_CMD2/ZERO>,.validity=<.GTR[.TIME1, 0]>
    ZERO =           0
    READ =           8
    WRITE =          9
    POP =            A
    PUSH =           B
    READ_LOCK =      C
    WRITE_UNLOCK =   D
    INCR =			 D	
    BIT_WR =         E
    UNLOCK =         F


.toc "   XFER_REG:  specifies the transfer register associated with this ref"
XFER_REG/=<22:20>,.default=<XFER_REG/-->,.validity=<.GTR[.TIME1, 0]>
    -- =             0

.toc "   PRIORITY_QUEUE:  specifies that ref is destined for the high priority queue"
PRIORITY_QUEUE/=<25>,.default=<PRIORITY_QUEUE/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =       0
    PRIORITY =    1

.toc "   ORDER_QUEUE:  specifies that ref is destined for order queue"
ORDER_QUEUE/=<24>,.default=<ORDER_QUEUE/ORDERED>,.validity=<.GTR[.TIME1, 0]>
    ORDERED =       0
    UNORDERED =     1

.toc "   SCRATCH_PAD:  specifies a scratch pad ref when lower bits indicate an sram ref"
SCRATCH_PAD/=<23>,.default=<SCRATCH_PAD/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =       0
    TRUE =        1

.toc "   REF_CNT:  specifies number of contiguous words this ref represents"
REF_CNT/=<28:26>,.default=<REF_CNT/0>,.validity=<.GTR[.TIME1, 0]>
    0 =             0
    1 =             1
    2 =             2
    3 =             3
    4 =             4
    5 =             5
    6 =             6
    7 =             7
    word_cnt_1 =    0
    word_cnt_2 =    1
    word_cnt_3 =    2
    word_cnt_4 =    3
    word_cnt_5 =    4
    word_cnt_6 =    5
    word_cnt_7 =    6
    word_cnt_8 =    7
    set_bits =      1
    clear_bits =    0
    test_and_set_bits =   3
    test_and_clear_bits = 2
    any_queue =     0
    order_queue =   1


; bits <19:17> for the mem instruction are coded as follows:
; this implies the following mutual exclusions:
;       signal <--> swap   (a signal is implies by swap)
;       chain <--> defer   (can't chain when you're ctx swapping, which is when defer can be spec'd)

        000:   no signal; no chain
        001:   no signal; chain
        010:   signal; no chain
        011:   signal; chain
        110:   swap; defer 0
        111:   swap; defer 1
        100:   volun swap; defer 0
        101:   volun swap; defer 1


.toc "   CTX_SWAP:  specifies that a context swap should occur after this uword"
CTX_SWAP/=<19>,.default=<CTX_SWAP/NO_SWAP>,.validity=<.GTR[.TIME1, 0]>
    NO_SWAP = 0
    SWAP =    1

.toc "   VOLUNTARY_SWAP:  specifies that this context should be swapped only if another thread is good to go"
VOLUNTARY_SWAP/=<18>,.default=<VOLUNTARY_SWAP/TRUE>,.validity=<.GTR[.TIME1, 0]>
    FALSE = 1
    TRUE =  0

.toc "   SIG_DONE:  specifies that this context should be signaled when mem ref completes"
SIG_DONE/=<18>,.default=<SIG_DONE/NO_SIG_DONE>,.validity=<.GTR[.TIME1, 0]>
    NO_SIG_DONE = 0
    SIG_DONE =    1

.toc "   CHAIN_REF:  specifies that subsequent mem ref should be grouped with current when performing mem op"
CHAIN_REF/=<17>,.default=<CHAIN_REF/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =    0
    TRUE =     1

.toc "   MEM_DEFER:  specifies cycle deferment on mem ref"
MEM_DEFER/=<17>,.default=<MEM_DEFER/0>,.validity=<.GTR[.TIME1, 0]>
    0 =    0
    1 =    1

.toc "   INDIRECT_REF:  specifies that subsequent mem ref should be grouped with current when performing mem op"
INDIRECT_REF/=<6>,.default=<INDIRECT_REF/FALSE>,.validity=<.GTR[.TIME1, 0]>
    FALSE =    0
    TRUE =     1





;------------- FIELDS SPECIFIC TO BRANCH FORMAT -------------

; branch target automatically filled in by compiler
.toc "   BRANCH_FIELD"
BRANCH_FIELD/=<16:7>,.address,.validity=<.GTR[.TIME1, 0]>

.toc "   BRANCH_TYPE:  specifies type of branch to be performed"
BRANCH_TYPE/=<28:25>,.default=<BRANCH_TYPE/EQSZ>,.validity=<.GTR[.TIME1, 0]>
    EQSZ =          0
    NEQZ =          1
    LESZ =          2
    GEQZ =          3
    COUT =          4
    NOT_COUT =      5
    GTRZ =          6
    LEQZ =          7
    CTX =           8
    NOT_CTX =       9
    MEMLOCK =       10.
    UNCOND =        12.
	EXTENDED =		15.

.toc "   EXT_BRANCH_TYPE:  extended field to BRANCH_TYPE field"
EXT_BRANCH_TYPE/=<20:17>,.default=<EXT_BRANCH_TYPE/SRAM>,.validity=<.GTR[.TIME1, 0]>
	SRAM =				 0
	SDRAM =				 1
	FBI =				 2
	INTER_THREAD =		 3
	AUTO_PUSH =			 4
	START_RECEIVE =		 5
	SEQ_NUM1 =			 6
	SEQ_NUM2 =			 7
	PCI =                8
	GET_Q_AVAIL =		 B
	PUT_Q_AVAIL =		 C
	REC_REQ_AVAIL =		 D
	PUSH_PROTECT =		 E
	PAR_ERR =			 F

.toc "   GUESS_BRANCH:  specifies whether to guess branch taken or not taken"
GUESS_BRANCH/=<4>,.default=<GUESS_BRANCH/NOT_TAKEN>,.validity=<.GTR[.TIME1, 0]>
    NOT_TAKEN =     0
    TAKEN =         1

.toc "   DEFER_BRANCH:  specifies whether the one uword after the branch completes before the branch does"
DEFER_BRANCH/=<6:5>,.default=<DEFER_BRANCH/0>,.validity=<.GTR[.TIME1, 0]>
    0 =         0
    1 =         1
    2 =         2 
    3 =         3

.toc "   BRANCH_PIPE:  specifies what pipe stage branch should be evaluated in"
BRANCH_PIPE/=<22:21>,.default=<BRANCH_PIPE/1>,.validity=<.GTR[.TIME1, 0]>
    1 =         0
    2 =         1 
    3 =         2

.toc "   BRANCH_CTX_MASK:  specifies context value to compare against when performing context-related branches"
BRANCH_CTX_MASK/=<24:23>,.default=<BRANCH_CTX_MASK/0>,.validity=<.GTR[.TIME1, 0]>
    0 =   0
    1 =   1
    2 =   2
    3 =   3


;------------- FIELDS SPECIFIC TO BRANCH ON BIT FORMAT -------------

.toc "   BBS_SHIFT:  specifies left shift amt for BBS instruction"
BBS_SHIFT/=<28:27,20:18>,.default=<BBS_SHIFT/0>,.validity=<.GTR[.TIME1, 0]>
    0 =     1.
	1 =		2.
	2 =		3.
	3 =		4.
	4 =		5.
	5 =		6.
	6 =		7.
	7 =		8.
	8 =		9.
	9 =		10.
    10 =    11.
	11 =	12.
	12 =	13.
	13 =	14.
	14 =	15.
	15 =	16.
	16 =	17.
	17 =	18.
	18 =	19.
	19 =	20.
    20 =    21.
	21 =	22.
	22 =	23.
	23 =	24.
	24 =	25.
	25 =	26.
	26 =	27.
	27 =	28.
	28 =	29.
	29 =	30.
    30 =    31.