📄 source5.uci
字号:
.toc------------------------------------------------------------------------------------------------------------
.toc
.toc I N T E L P R O P R I E T A R Y
.toc
.toc COPYRIGHT (c) 1998-1999 BY INTEL CORPORATION. ALL RIGHTS
.toc RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
.toc BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
.toc RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
.toc LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
.toc MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
.toc THE PRIOR WRITTEN PERMISSION OF :
.toc
.toc INTEL CORPORATION
.toc
.toc 2200 MISSION COLLEGE BLVD
.toc
.toc SANTA CLARA, CALIFORNIA 95052-8119
.toc
.toc
.toc-------------------------------------------------------------------------------------------------------------
.ucode_size 1024
.rtol ;bit 0 is lsb
.hexadecimal ;hexidecimal radix
.sequential ;sequential allocation
.dcode
.version 7/2/1998
.width/32 ; set width of microword
.toc ""
.toc "MICROCODE RESTRICTIONS"
.toc ""
.toc ""
.toc "MICROCODE FIELD EXCLUSIVITY"
.toc ""
.toc ""
.toc "RAM ACCESS"
.toc ""
.toc ""
.toc ""
.toc "RULES FOR MODIFYING CODE"
.toc ""
.toc " "
.toc ""
.toc "Field Definitions"
; the following bit definition is not part of actual microword
DUMMY/=<99>,.default=<DUMMY/DUMMY>
DUMMY = 0
DUMMY1 = 1
;------------- FIELDS SHARED AMONG SEVERAL UWORD FORMATS -------------
.toc " UW_TYPE: specifies basic uword format type"
UW_TYPE1/=<31:30>,.default=<UW_TYPE1/ALU_SHIFT>,.validity=<.GTR[.TIME1, 0]>
ALU_SHIFT = 0, 1 ; 3-operand load family w/ shifter op: dest = ALU_OP(A, SHIFT(B))
.toc " UW_TYPE: specifies basic uword format type"
UW_TYPE/=<31:29>,.default=<UW_TYPE/NONE>,.validity=<.GTR[.TIME1, 0]>
NONE = 0, 1
BR_ALU = 2, 1 ; 3-operand load family: dest = ALU_OP(A, B) where either A or B is immediate data
BR_BYTE = 3, 1 ; either ALU operation or issue mem ref by forming address from A + B
ALU = 4, 1 ; 3-operand load family: dest = ALU_OP(A, B) where both A and B are registers
EXT_2_SRC = 5, 1 ; extended opcodes with 2 source operands; look at EXT_2_OP_CMDx to further decode instruction
IMMED = 6, 1 ; load 16-bit immediate data into dest reg
EXT_1_SRC = 7, 1 ; extended opcodes with 1 source operand; look at EXT_1_OP_CMD to further decode instruction
.toc " EXT_1_OP_CMD: specifies type of extended uword format type"
EXT_1_OP_CMD/=<3:0>,.default=<EXT_1_OP_CMD/CSR>,.validity=<.GTR[.TIME1, 0]>
CSR = 0, 1 ; CSR rd/wr cmd
FAST_WR = 2, 1 ; fast write (data in ref packet)
HASH = 3, 1 ; HASH cmd
CONTEXT = 4, 1 ; set context control format
BRANCH_BIT =5 , 1 ; branch on a specified bit of a B bank reg
USTORE = 6, 1 ; write the control store
BRANCH = 7, 1 ; branch uword
FBOX_CSR = 8., 1 ; fbox csr read/write
.toc " EXT_1_OP_CMD_QUAL: qualifies type of extended 1 op cmd"
EXT_1_OP_CMD_QUAL/=<4>,.default=<EXT_1_OP_CMD_QUAL/READ>,.validity=<.GTR[.TIME1, 0]>
READ = 0, 1 ;
WRITE = 1, 1 ;
.toc " ALU_OP: specifies type of ALU operation"
ALU_OP/=<3:0>,.default=<ALU_OP/B>,.validity=<.GTR[.TIME1, 0]>
B = 0., 1
~B = 1, 1
AND = 2, 1
AND~ = 3, 1
~AND = 4, 1
XOR = 5., 1
OR = 6, 1
+IFSIGN = 7, 1
- = 8, 1
B-A = 9., 1
+4 = 10., 1
+8 = 12., 1
+16 = 13., 1
+ = 14., 1
+CARRY = 15., 1
.toc " REL_A_OP: specifies a relative A operand register address"
REL_A_OP/=<16:12>,.default=<REL_A_OP/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
reg = 00
_DEFAULT_VALUE_ = 0
-- = 0
@UINT
.toc " ABS_A_OP: specifies an absolute A operand register address"
ABS_A_OP/=<19:12>,.default=<ABS_A_OP/-->,.validity=<.GTR[.TIME1, 0]>
reg = 80
-- = 0
@UINT
.toc " A_IMMED_DATA_5_BIT: specifies an immediate A operand"
A_IMMED_DATA_5_BIT/=<16:12>,.default=<A_IMMED_DATA_5_BIT/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
@UINT
.toc " B_IMMED_DATA_5_BIT: specifies an immediate B operand"
B_IMMED_DATA_5_BIT/=<11:7>,.default=<B_IMMED_DATA_5_BIT/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
@UINT
.toc " IMMED_DATA_11_BIT: specifies an immediate A operand"
IMMED_DATA_11_BIT/=<17:7>,.default=<IMMED_DATA_11_BIT/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
@UINT
.toc " CSR_ADDRESS: specifies immediate CSR address: NOTE: if msb is set ==> SRAM CSR space"
CSR_ADDRESS/=<5,16:7>,.default=<CSR_ADDRESS/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
THREAD_DONE_REG0 = 2
THREAD_DONE_REG1 = 3
CYCLE_CNT = 4
RCV_CNTL = 6
RCV_REQ = 7
SOP_SEQ1 = 8
SOP_SEQ2 = 9
ENQUEUE_SEQ1 = A
ENQUEUE_SEQ2 = B
REC_FASTPORT_CTL = C
RCV_RDY_CNT = 30
RCV_RDY_LO = 31
RCV_RDY_HI = 32
XMIT_PTR = 38
XMIT_RDY_LO = 39
XMIT_RDY_HI = 3A
RCV_RDY_CTL = 3E
XMIT_RDY_CTL = 3F
HASH_48 = 40
HASH_64 = 41
HASH_MULTIPLIER_64_LO = 50
HASH_MULTIPLIER_64_HI = 51
HASH_MULTIPLIER_48_LO = 52
HASH_MULTIPLIER_48_HI = 53
RDYBUS_TEMPLATE_CTL = 60
RDYBUS_TEMPLATE_PROG1 = 61
RDYBUS_TEMPLATE_PROG2 = 62
RDYBUS_TEMPLATE_PROG3 = 63
RDYBUS_SYNCH_COUNT_DEFAULT = 64
FLOWCTL_MASK = 65
SEND_CMD = 66
RFIFO_ADDR = 67
FP_READY_WAIT = 69
GET_CMD = 6C
SELF_DESTRUCT = 75
IREG = 78
; SRAM CSR SPACE
SRAM_AUTO_BASE = 404
SRAM_AUTO_PTR = 408
SRAM_AUTO_PTR_MSK = 40C
SRAM_AUTO_TEST_MOD = 410
.toc " FAST_WR_ADDRESS: specifies immediate FAST WRITE address: NOTE: if msb is set ==> SRAM CSR space"
FAST_WR_ADDRESS/=<5,16:7>,.default=<FAST_WR_ADDRESS/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
INTER_THD_SIG = 70
THREAD_DONE = 71
THREAD_DONE_INCR1 = 72
THREAD_DONE_INCR2 = 73
XMIT_VALIDATE = 74
SELF_DESTRUCT = 75
INCR_ENQ_NUM1 = 76
INCR_ENQ_NUM2 = 77
IREG = 78
.toc " FAST_WR_DATA: specifies fast write data"
FAST_WR_DATA/=<26:17>,.default=<FAST_WR_DATA/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
@UINT
;.toc " IMMED_B_DATA: specifies an immediate A operand"
;IMMED_B_DATA/=<5,13:7>,.default=<IMMED_B_DATA/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
; _DEFAULT_VALUE_ = 0
; @UINT
.toc " REL_B_OP: specifies a relative B operand register address"
REL_B_OP/=<11:7>,.default=<REL_B_OP/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
_DEFAULT_VALUE_ = 0
-- = 0
@UINT
.toc " AB_REL_SRC: specifies a relative A or B operand register address"
AB_REL_SRC/=<26:21>,.default=<AB_REL_SRC/_DEFAULT_VALUE_>,.validity=<.GTR[.TIME1, 0]>
reg = 00
_DEFAULT_VALUE_ = 0
@UINT
.toc " ABS_B_OP: specifies an absolute B operand register address"
ABS_B_OP/=<6:4,11:7>,.default=<ABS_B_OP/-->,.validity=<.GTR[.TIME1, 0]>
-- = 0
@UINT
.toc " REL_DEST: specifies a relative destination register address"
REL_DEST/=<26:21>,.default=<REL_DEST/-->,.validity=<.GTR[.TIME1, 0]>
reg = 00
-- = 30
.toc " ABS_DEST: specifies an absolute destination register address"
ABS_DEST/=<28:21>,.default=<ABS_DEST/-->,.validity=<.GTR[.TIME1, 0]>
reg = C0
-- = F0
.toc " IMMED_OP: specifies whether to interpret absolute or relative A operand as immediate data"
IMMED_OP/=<5>,.default=<IMMED_OP/FALSE>,.validity=<.GTR[.TIME1, 0]>
FALSE = 0
TRUE = 1
.toc " AB_IMMED: specifies whether to interpret absolute or relative B operand as immediate data"
AB_IMMED/=<4>,.default=<AB_IMMED/A>,.validity=<.GTR[.TIME1, 0]>
A = 0
B = 1
;------------- FIELDS SPECIFIC TO ALU/SHIFT FORMAT -------------
.toc " SHIFT_AMT: specifies number of bit shifts in shifter"
SHIFT_AMT/=<28:27,20:18>,.default=<SHIFT_AMT/INDIRECT>,.validity=<.GTR[.TIME1, 0]>
INDIRECT = 0
0 = 0
1 = 1
2 = 2
3 = 3
4 = 4
5 = 5
6 = 6
7 = 7
8 = 8
9 = 9
10 = 10.
11 = 11.
12 = 12.
13 = 13.
14 = 14.
15 = 15.
16 = 16.
17 = 17.
18 = 18.
19 = 19.
20 = 20.
21 = 21.
22 = 22.
23 = 23.
24 = 24.
25 = 25.
26 = 26.
27 = 27.
28 = 28.
29 = 29.
30 = 30.
31 = 31.
;.toc " ROTATE: specifies whether to rotate or shift in shifter"
;ROTATE/=<29>,.default=<ROTATE/SHIFT>,.validity=<.GTR[.TIME1, 0]>
; SHIFT = 0
; ROTATE = 1
.toc " SHIFT_CNTL: specifies left rotate, or left/right shift or double shift"
SHIFT_CNTL/=<17,6>,.default=<SHIFT_CNTL/LEFT_ROT>,.validity=<.GTR[.TIME1, 0]>
LEFT_ROT = 0
RIGHT = 1
LEFT = 2
DBL_SHF = 3
.toc " OPERAND_SWAP: specifies A-B operand swap"
ALU_SHF_OP_SWAP/=<29>,.default=<ALU_SHF_OP_SWAP/FALSE>,.validity=<.GTR[.TIME1, 0]>
FALSE = 0
TRUE = 1
;------------- FIELDS SPECIFIC TO ALU FORMAT -------------
.toc " ALU_OPERAND_SWAP: specifies A-B operand swap"
ALU_OP_SWAP/=<20>,.default=<ALU_OP_SWAP/FALSE>,.validity=<.GTR[.TIME1, 0]>
FALSE = 0
TRUE = 1
;------------- FIELDS SPECIFIC TO LOAD_FIELD FORMAT -------------
.toc " BYTE_MASK: specifies byte enable load mask"
BYTE_MASK/=<24:21>,.default=<BYTE_MASK/0>,.validity=<.GTR[.TIME1, 0]>
0 = 0
0001 = 1
0010 = 2
0011 = 3
0100 = 4
0101 = 5
0110 = 6
0111 = 7
1000 = 8
1001 = 9
1010 = A
1011 = B
1100 = C
1101 = D
1110 = E
1111 = F
;.toc " NYB_SHIFT_AMT: specifies shift amt in multiple of nybbles"
;NYB_SHIFT_AMT/=<22:20>,.default=<NYB_SHIFT_AMT/0>,.validity=<.GTR[.TIME1, 0]>
; 0 = 0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -