urt_defs.h

Nucleus Kernel Demo Full source code

/*************************************************************************/
/*                                                                       */
/*        Copyright (c) 1999-2000  Accelerated Technology, Inc.          */
/*                                                                       */
/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the      */
/* subject matter of this material.  All manufacturing, reproduction,    */
/* use, and sales rights pertaining to this subject matter are governed  */
/* by the license agreement.  The recipient of this software implicitly  */
/* accepts the terms of the license.                                     */
/*                                                                       */
/*************************************************************************/

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                            VERSION          */
/*                                                                       */
/*      urt_defs.h                                     ARM 6/7/9 1.11.19 */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/*      UART                                                             */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*      This file contains constant definitions and function macros      */
/*      for the UART module.                                             */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*    M. Kyle Craig , Accelerated Technology, Inc.                       */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*      none                                                             */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*      none                                                             */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*  M. Kyle Craig       02/05/99        Created Initial Version for PID  */
/*  George Clark        02/05/99        Verified Initial Version for PID */
/*  B. Whatley          08-12-1999	Released version 1.11.18         */
/*  D. Phillips         01-18-2000      Updated port to new structuring  */
/*                                       scheme                          */
/*									 */	
/*************************************************************************/
#ifndef URT_DEFS
#define URT_DEFS


/*
 * Layout of the Serial controller; from our perspective, each
 * byte-wide register in the serial chip is on a word boundary
 * On a big-endian machine, we need to offset I/O addresses by 3
 * (unfortunately, there is no byte-lane steering on APB, so we
 * have to do it here in software =8( ).
 */

typedef struct UART_STRUCT
{
#ifdef BIG_ENDIAN
    volatile unsigned char _BEpad[3];
#endif
    volatile unsigned char rhrthr;
    volatile unsigned char _pad0[3];
    volatile unsigned char ier;
    volatile unsigned char _pad1[3];
    volatile unsigned char isrfcr;
    volatile unsigned char _pad2[3];
    volatile unsigned char lcr;
    volatile unsigned char _pad3[3];
    volatile unsigned char mcr;
    volatile unsigned char _pad4[3];
    volatile unsigned char lsr;
    volatile unsigned char _pad5[3];
    volatile unsigned char msr;
    volatile unsigned char _pad6[3];
    volatile unsigned char spr;
} UART;
#define rhr             rhrthr
#define thr             rhrthr
#define isr             isrfcr
#define fcr             isrfcr

#define dll             rhrthr
#define dlm             ier

/*******************************************************************************/
/* Interrupt Enable Register - IER                                             */
/*******************************************************************************/
#define IER_Rx_Holding_Reg  0x01   /* b0 - Recieve Holding Register Interrupt  - Enabled When Set   */
#define IER_Tx_Holding_Reg  0x02   /* b1 - Transmit Holding Register Interrupt - Enabled When Set   */
#define IER_Rx_Line_Stat    0x04   /* b2 - Receiver Line Status Interrupt      - Enabled When Set   */
#define IER_Modem_Status    0x08   /* b3 - Modem Status Register Interrupt     - Enabled When Set   */
                                   /* b7 - b4 are not used and are set to zero                      */

/*******************************************************************************/
/* FIFO Control Register - FCR                                                 */
/*******************************************************************************/
#define FCR_Fifo_Enable     0x01   /* b0 - Tx and Rx FIFO Enable               - Enabled When Set   */
#define FCR_Rx_Fifo_Reset   0x02   /* b1 - Clear Rx FIFO and reset its counter - Clears When Set    */
#define FCR_Tx_Fifo_Reset   0x04   /* b2 - Clear Tx FIFO and reset its counter - Clears When Set    */
#define FCR_DMA_Mode_Select 0x08   /* b3 - Change DMA Mode State from m0 to m1 - Mode 1 When Set    */

/* FCR b7 - b6 FIFO Trigger Level  */
 
#define FCR_Rx_Trig_Lvl_01  0x00   /* 0 0 - FIFO Rx Trigger Level 01 */              
#define FCR_Rx_Trig_Lvl_04  0x40   /* 0 1 - FIFO Rx Trigger Level 04 */          
#define FCR_Rx_Trig_Lvl_08  0x80   /* 1 0 - FIFO Rx Trigger Level 08 */
#define FCR_Rx_Trig_Lvl_16  0xc0   /* 1 1 - FIFO Rx Trigger Level 16 */

/*******************************************************************************/
/*  Latch Control Register - LCR                                               */
/*******************************************************************************/

/* LCR b2 defines the stop bits setup b1 - b0 define the Tx - Rx Word Length                        */
/* The following defines cover all of the available options                                         */

#define LCR_5_Bit_Word_1    0x00   /* 0 0 0  - 5 Bit Word - 1 Stop Bit   */
#define LCR_6_Bit_Word_1    0x01   /* 0 0 1  - 6 Bit Word - 1 Stop Bit   */ 
#define LCR_7_Bit_Word_1    0x02   /* 0 1 0  - 7 Bit Word - 1 Stop Bit   */
#define LCR_8_Bit_Word_1    0x03   /* 0 1 1  - 8 Bit Word - 1 Stop Bit   */
#define LCR_5_Bit_Word_1p5  0x04   /* 1 0 0  - 5 Bit Word - 1.5 Stop Bit */
#define LCR_6_Bit_Word_2    0x05   /* 1 0 1  - 6 Bit Word - 2 Stop Bit   */
#define LCR_7_Bit_Word_2    0x06   /* 1 1 0  - 6 Bit Word - 1 Stop Bit   */
#define LCR_8_Bit_Word_2    0x07   /* 1 1 1  - 6 Bit Word - 1 Stop Bit   */


/* Code below is to split apart Word Length and Stop Bits */

#define LCR_5_Bit_Word    0x00   /* 0 0  - 5 Bit Word   */
#define LCR_6_Bit_Word    0x01   /* 0 1  - 6 Bit Word   */ 
#define LCR_7_Bit_Word    0x02   /* 1 0  - 7 Bit Word   */
#define LCR_8_Bit_Word    0x03   /* 1 1  - 8 Bit Word   */

#define LCR_Stop_Bit_1	    0x000  /* 1 stop bit */
#define LCR_Stop_Bit_1p5    0x100  /* 1 1/2 stop bit */
#define LCR_Stop_Bit_2	    0x100  /* 2 stop bit */

#define LCR_Parity_Enable   0x08   /* b3 - Enable Parity Bit Generation and Check - Enabled When Set */
#define LCR_Parity_Even     0x10   /* b4 - Odd/Even Parity Generation and Check   - Even When Set    */
#define LCR_Parity_Set      0x20   /* b5 - Toggle Generated Parity Bit 0/1        - 0 When Set       */
#define LCR_Break_Set       0x40   /* b6 - Force Break Control ( Tx o/p low)      - Forced When Set  */
#define LCR_Divisor_Latch   0x80   /* b7 - Enable Internal Baud Rate Latch        - Enabled When Set */

/*******************************************************************************/
/* Modem Control Register - MCR                                                */
/*******************************************************************************/

#define MCR_DTR_Low         0x01   /* b0 - Set DTR Signal Low/High - DTR Low when Set */
#define MCR_RTS_Low         0x02   /* b1 - Set RTS Signal Low/High - RTS Low when Set */
                                   /* MCR b2 is not used                              */
#define MCR_Interrupt_En    0x08   /* b3 - Interrupt output pin Operate/3-State  - Operate when Set */
#define MCR_Loopback_Mode   0x10   /* b4 - Loopback(Test) Mode Enable            - Enabled When Set */

/* The Following Registers are Status Registers which Report conditions within the UART/PPP during  *
 * operation. The defined values are masks to ensure that the register flags are correctly accessed */

/*******************************************************************************/
/* Interrupt Status Register - ISR                                             */
/*******************************************************************************/

/* ISR b0 indicates that an interrupt is pending when clear. b3 - b1 signal which interrupt as per:- */

#define ISR_LSR_Source      0x06   /* 0 1 1 - Receiver Line Status Register Priority 1 */
#define ISR_Rx_Rdy_Source   0x04   /* 0 1 0 - Received Data Ready           Priority 2 */
#define ISR_Rx_Rdy_TO_Src   0x0c   /* 1 1 0 - Received Data Ready Time Out  Priority 2 */
#define ISR_Tx_Rdy_Source   0x02   /* 0 0 1 - Transmitter Holding Reg Empty Priority 3 */
#define ISR_MODEM_Source    0x00   /* 0 0 0 - Modem Status Register         Priority 4 */

/* ISR b7 - b4 are not used - in st16c552 b7 - b6 are Set b5 - b4 are Clear   */

/*******************************************************************************/
/* Line Status Register - LSR                                                                              */
/*******************************************************************************/

#define LSR_Rx_Data_Ready   0x01   /* b0 - Data Recieved and Saved in Holding Reg - Set when Valid */
#define LSR_Overrun_Error   0x02   /* b1 - Overrun Error Occured                  - Set When Valid */
#define LSR_Parity_Error    0x04   /* b2 - Received Data has Incorrect Parity     - Set When Valid */
#define LSR_Framing_Error   0x08   /* b3 - Framing Error (No Stop Bit)            - Set When Valid */
#define LSR_Break_Interrupt 0x10   /* b4 - Break Signal Received                  - Set When Valid */
#define LSR_Tx_Hold_Empty   0x20   /* b5 - Tx Holding Register is empty and ready - Set When Valid */
#define LSR_Tx_Fifo_Empty   0x40   /* b6 - Tx Shift Registers and FIFO are Empty  - Set When Valid */
#define LSR_Fifo_Error      0x80   /* b7 - At Least one of b4 - b2 has occurred   - Set When Valid */

/*******************************************************************************/
/* Modem Status Register - MSR                                                 */
/*******************************************************************************/
/* */
/* ---------------------       */

#define MSR_CTS_Change      0x01   /* b0 - Set When CTS Input has Changed State */
#define MSR_DSR_Change      0x02   /* b1 - Set When DSR Input has Changed State */
#define MSR_RI_Change       0x04   /* b2 - Set When RI  Input has Changed State */
#define MSR_CD_Change       0x08   /* b3 - Set When CD  Input has Changed State */
#define MSR_CTS_Lp_State    0x10   /* b4 - RTS Equivalent during loopback - inverse of CTS */
#define MSR_DSR_Lp_State    0x20   /* b5 - DTR Equivalent during loopback - inverse of DSR */
#define MSR_RI_Lp_State     0x40   /* b6 - MCR b2 Equivalent during loopback - inverse of RI */
#define MSR_CD_Lp_State     0x88   /* b7 - INT EN Equivalent during loopback - inverse of CD */

/*******************************************************************************/
/* ScratchPad Register - SPR                                                   */
/*******************************************************************************/

/* This is a user register for any required bit storage required */

#define SPR_User_0          0x01
#define SPR_User_1          0x02
#define SPR_User_2          0x04
#define SPR_User_3          0x08
#define SPR_User_4          0x10
#define SPR_User_5          0x20
#define SPR_User_6          0x40
#define SPR_User_7          0x80

/*******************************************************************************/
/*Divisor Latch Lower and Upper Byte Values - DLL DLM                          */