fp240.asm

自己编写的tms320f240的烧写程序

SYSSR .set 0701Ah ; System Module Status Register
WDCR .set 07029h ; WDT Control reg
DP_PF1 .set 224 ; 7000h/80h = 100h or 224
  .globl _wdtoff
  .text
  .def _wdtoff
_wdtoff: ; presume ARP = AR1 (SP)
*****************************************************************************
* On entry, presume ARP = AR1 (SP) *
* *
* Step 1. Pop the return address off the h/w stack and push to s/w stack *
*****************************************************************************
   POPD *+ ; pop return address, push on software stack
; ARP=AR1, SP=SP+1
*****************************************************************************
* Step 2. Push the frame pointer onto s/w stack *
*****************************************************************************
   SAR AR0,*+ ; push AR0 (FP) onto SP
; ARP=AR1, SP=SP+2
*****************************************************************************
* Step 3. Allocate the local frame *
*****************************************************************************
  SAR AR1,* ; *SP = FP
  LAR AR0,#1 ; FP = size of local frame, 1
  LAR AR0,*0+ ; FP = SP, SP += size ==> allocate frame
*****************************************************************************
* Step 5. Begin code that will disable the WDT *
*****************************************************************************
  LDP #DP_PF1 ; Page DP_PF1 includes WET through EINT frames
  LACL WDCR ; ACC = WDTCR, watchdog timer control register

  OR #06fh ; set WDDIS bit and WDCHK2:0 bits, WDCLK to max.
  SACL WDCR ; write ACC out to WDTCR
*****************************************************************************
* Step 9. Deallocate the local frame *
*****************************************************************************
  SBRK 1+1 ; deallocate frame, point to saved FP
***************************************************************************
* Step 10. restore the frame pointer *
*****************************************************************************
  LAR AR0,*-; pop FP
***************************************************************************
* Step 11. copy the return address from the s/w stack and push onto h/w *
* stack *
***************************************************************************
   PSHD * ; push return address on h/w stack
   RET ; return
 
  
SYSSR .set 0701Ah
SYSCR .set 07018h
WDTCR .set 07029h ;WD Control reg
CKCR0 .set 0702ah ;PLL Clock Control Register 0
CKCR1 .set 0702ch ;PLL Clock Control Register 1
DP_PF1 .set 224
  .globl _c240init
  .text
  .def _c240init
_c240init: ; presume ARP = AR1 (SP)**
***************************************************************************
* On entry, presume ARP = AR1 (SP) *
* *
* Step 1. pop the return address off the h/w stack and push to s/w stack *
*****************************************************************************
  POPD *+ ; pop return address, push on software stack
; ARP=AR1, SP=SP+1
*****************************************************************************
* Step 2. push the frame pointer onto s/w stack *
*****************************************************************************
  SAR AR0,*+ ; push AR0 (FP) onto SP
; ARP=AR1, SP=SP+2
*****************************************************************************
* Step 3. Allocate the local frame *
*****************************************************************************
  SAR AR1,* ; *SP = FP
  LAR AR0,#1 ; FP = size of local frame, 1
  LAR AR0,*0+ ; FP = SP, SP += size ==> allocate frame

* Step 5. begin code that will initialize the ’240 registers *
*****************************************************************************
  CLRC SXM ; Clear Sign Extension Mode
  CLRC OVM ; Reset Overflow Mode
* Set Data Page pointer to page 1 of the peripheral frame
  LDP #DP_PF1 ; Page DP_PF1 includes WET through EINT frames
* Clear system status register reset bits (PORRST, ILLADR, SWRST, & WDRST)
  LACL #020h ; load mask pattern to clear rst flags
  SACL SYSSR ; write ACC to SYSSR
* Set Watchdog timer period to 1 second
  LACL #02Fh ; set WDCHK2 & 0 bits, WDCLK divider to max (1s)
  SACL WDTCR ; write ACC out to WDTCR
* Configure PLL for 4–MHz xtal, 10–MHz SYSCLK, and 20–MHz CPUCLK
* SPLK #00E4h,CKCR1 ;CLKIN(XTAL)=4 MHz,CPUCLK=20 MHz
* SPLK #00C3h,CKCR0 ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2
* Configure PLL for 10–MHz osc, 10–MHz SYSCLK, and 20–MHz CPUCLK
  SPLK #00B1h,CKCR1 ;CLKIN(OSC)=10 MHz,CPUCLK=20 MHz
  SPLK #00C3h,CKCR0 ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2
* Set VCCAON bit and CLKSRC1:0; leave other bits at their reset values.
  SPLK #40C8h,SYSCR ; SYSCR <= 40C8h
***************************************************************************
* Step 9. Deallocate the local frame *
***************************************************************************
  SBRK 1+1 ; deallocate frame, point to saved FP
***************************************************************************
* Step 10. restore the frame pointer *
***************************************************************************
  LAR AR0,*- ; pop FP
***************************************************************************
* Step 11. copy the return address from the s/w stack and push onto h/w *
* stack *
***************************************************************************
  PSHD * ; push return address on h/w stack
  RET ; return
  .end