dsp281x_ini.c

自己编写的dsp2812的小程序,大家看看,希望对大家有帮助.

    SCIFFRXA  = 0x0000; // reset transmit chanel
    SCICCRA   = 0x07;   // one stop bit;no parity;8 bit Data
    SCICTL1A  = 0x03;
    SCIHBAUDA = SCIABAUDH;
    SCILBAUDA = SCIABAUDL;
    SCICTL2A  = 0x03;   // Enable RI,TI
    SCICTL1A  = 0x23;   // enable Recieve and Transmit
    SCIFFTXA  = 0xC020; // Enable interrupt, Triger level set to min
    SCIFFRXA  = 0x601F; // disable interrupt, Triger Level set to max
    SCIFFCTA  = 0x0008;
    SCIPRIA   = 0x0000;
    //setup SCIB
    SCIFFTXB  = 0x0000; // reset transmit chanel
    SCIFFRXB  = 0x0000; // reset transmit chanel
    SCICCRB   = 0x07;   // one stop bit;no parity;8 bit Data
    
    SCICTL1B  = 0x03;
    SCIHBAUDB = SCIBBAUDH;
    SCILBAUDB = SCIBBAUDL;
    SCICTL2B  = 0x03;   // Enable RI,TI
    SCICTL1B  = 0x23;   // enable Recieve and Transmit
    
    SCIFFTXB  = 0xC020; // Enable TX Interrupt
    SCIFFRXB  = 0x3069; // enable RX Interrupt, Triger Level set to 9 
    SCIFFCTB  = 0x0008;
    SCIPRIB   = 0x0000;
}

//===========================================================================
// AdcInit:
// This function initializes the ADC to a known state.
//===========================================================================

void AdcInit()
{
//	extern void DSP28x_usDelay(uint32 Count);
	
    // To powerup the ADC the ADCENCLK bit should be set first to enable
    // clocks, followed by powering up the bandgap and reference circuitry.
    // After a 5ms delay the rest of the ADC can be powered up. After ADC
    // powerup, another 20us delay is required before performing the first
    // ADC conversion. Please note that for the delay function below to
    // operate correctly the CPU_CLOCK_SPEED define statement in the
    // DSP28_Examples.h file must contain the correct CPU clock period in
    // nanoseconds. For example:
	
    ADCTRL3 = 0x00C0;       // Power up bandgap/reference circuitry
    DELAY_US(ADC_usDELAY);  // Delay before powering up rest of ADC
    ADCTRL3 |= 0x0020;      // Power up rest of ADC
    DELAY_US(ADC_usDELAY2); // Delay after powering up ADC
    
    // Emulation suspend immediately stop
    // FCLKv = CLK/1
    // Continuous conversation mode
    // Cascaded sequencer operation
    ADCTRL1 = 0x3F10;       // Width of SOC pulse is 16 ADCCLK period, Start-stop mode
    ADCTRL3 |= 0x000C;      // HSPCLK/[12*(ADCTRL1[7] + 1)] = 12.5MHz
                            // Sequential sampling mode
    ADCTRL2 = 0x4900;       // Enable sequencer 1 interrupts, EVA start SEQ is allowed
    ADCMAXCONV = 0x0003;    // 4 channel AD sequence
    ADCCHSELSEQ1 = 0x3210;
//    ADCCHSELSEQ2 = 0x7654;
//    ADCCHSELSEQ3 = 0xBA98;
//    ADCCHSELSEQ4 = 0x0EDC; //SEQA0 - SEQA7,SEQB0 - SEQB6
    
}
//===========================================================================
// XintfInit:
// This function initializes the Xintf to a known state.
//===========================================================================

void XintfInit( void )
{
    XTIMING2 = 0x031229;
    XINTCNF2 = 0x10008;
    XBANK    = 0x0002;
}

//===========================================================================
// ECanInit: 
// This function initializes the eCAN module to a known state.
//===========================================================================

void ECanInit( void )
{
    // Only 32.bit accesses are allowed to the control and status registers. 
    // This restriction does not apply to the mailbox RAM area.
    EALLOW;
    CANTIOC = 0x00000008; // Configure eCAN RX and TX pins
    CANRIOC = 0x00000008; // for eCAN transmissions using eCAN regs
    CANMC = 0x00000000;   // Force the eCAN into SCC mode
    // Initialize all bits of 'Master Control Field' to zero
    // Some bits of MSGCTRL register come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero
    ECanaMboxes.MBOX0.MSGCTRL  = 0x00000000;  
    ECanaMboxes.MBOX1.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX2.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX3.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX4.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX5.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX6.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX7.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX8.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX9.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX10.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL = 0x00000000;
	// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution. 
	CANTA = 0xFFFFFFFF; // Clear all TAn bits
	CANRMP = 0xFFFFFFFF; // Clear all RMPn bits
    // Clear all interrupt flag bits
    CANGIF0 = 0xFFFFFFFF; 
	CANGIF1 = 0xFFFFFFFF; 
	// Configure bit timing parameters
    CANMC |= 0x00001000; // Set CCR(CANMC:12) = 1
	while ( (CANES&0x00000010) == 0) {} // Wait for CCE bit to be set..
	CANBTC = BITTIMING;
	CANMC &= 0xFFFFEFFF; // Set CCR(CANMC:12) = 0
	while ( (CANES&0x00000010) != 0) {} // Wait for CCE bit to be cleared..
	// Disable all Mailboxes
	CANMC |= 0x00000440; // Set CANMC[6, 10](STM, DBO) = 1, 1; Ecan is in self test mode
	CANME = 0x00000000;
	CANGIM = 0x00007F03; // Enable System INT to Level 0
	CANMIM = 0x00000008; // Enable Mailbox 3 INT
    EDIS;
}

void ECanConfig( void )
{
    CANTRR = 0x00000000;
    ECanaLAMRegs.LAM3 = 0xFFFC0000; // LAM3[31]=LAMI = 1; LAM3[18:28] = 11111111111b
    ECanaMboxes.MBOX1.MSGID = 0x00040000; // ID = 1;
    ECanaMboxes.MBOX3.MSGID = 0x40040000; // AME = 1; ID = 1; The corresponding acceptance mask is used.
    ECanaMboxes.MBOX1.MSGCTRL = 0x00000008;  // DLC = 8, 8 byte is Xmitted
    CANMD = 0x00000008; // Configure Mailbox 1 for Transmit; Mailbox 3 as Receive
	CANME |= 0x0000000A; // Enable Mailbox1 and Mailbox 3
	// Write data to be transmitted
	ECanaMboxes.MBOX1.MDL = 0x76543210;
	ECanaMboxes.MBOX1.MDH = 0xFEDCBA98;
    CANMIL = 0xFFFFFFFF; // Enable all Mailboxes INT to Level 1
}


//===========================================================================
// SpiInit:
// This function initializes the SPI to a known state.
//2005.4.28
//===========================================================================

void SpiInit( void )
{
    /* Initialize SPI FIFO registers , example from TI
   SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SCI

   SpiaRegs.SPICCR.all=0x001F;       //16-bit character, Loopback mode 
   SpiaRegs.SPICTL.all=0x0017;       //Interrupt enabled, Master/Slave XMIT enabled
   SpiaRegs.SPISTS.all=0x0000;
   SpiaRegs.SPIBRR=0x0063;           // Baud rate
   SpiaRegs.SPIFFTX.all=0xC028;      // Enable FIFO's, set TX FIFO level to 8
   SpiaRegs.SPIFFRX.all=0x0028;      // Set RX FIFO level to 31
   SpiaRegs.SPIFFCT.all=0x00;
   SpiaRegs.SPIPRI.all=0x0010;
    
   SpiaRegs.SPICCR.bit.SPISWRESET=1;  // Enable SCI

   SpiaRegs.SPIFFTX.bit.TXFIFO=1;
   SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
   */
    SPICCR &= 0xFF7F;		//Reset SPI
    SPICCR = 0x001F;		//16-bit data,looback mode
    SPICTL = 0x0017;		//Master Mode,Master/Slave XMIT enabled ,Interrupt enabled
    SPISTS = 0x0000;
    SPIBRR = 0x0000;		//Baud rate is LSPCLK/4 = CLKIN/16
    SPIFFTX = 0xC000;		//Enable FIFO, set TX FIFO level to 0
    SPIFFRX = 0x0030;		//Enable RXFIFO,set RXFIFO level to 16
    SPIFFCT	= 0x00;			//FIFO delay set to 0
    SPIPRI = 0x0010;		//ignore suspend
    
    SPICCR |= BIT7;			//enable SPI
    
    SPIFFTX |= BIT13;		//enable TX FIFO
    SPIFFRX |= BIT13;		//enable RX FIFO
}

/*void McbspInit(void)
{ 

	 uint16 i;	
	
	//发送器和接收器置于复位模式
	 SPCR1  = 0x0000;
	 SPCR2  = 0x0000;
	
	//McBSP设置为SPI主设备,Clkspt = 11b
	 SPCR1  = 0x1800;
	for(i = 0; i < 6; i++)
	 PCR  = 0x0b08;
	for(i = 0; i < 6; i++)
	 SRGR2  = 0x2000;  //clksm=1,fsgm=0
	for(i = 0; i < 6; i++)	
	 SRGR1  = 0x000A;  //分频系数
	for(i = 0; i < 6; i++)
	 XCR1  = 0x0040;
	 XCR2  = 0x0080;
	
	//使能采样速率生成器
	
	 SPCR2  |= 0x0040;
	
	for(i = 0; i < 100; i++)
		NOP;
	
	 SPCR1  = 0x1821;
	for(i = 0; i < 10; i++)
		NOP;
	 SPCR2  = 0x0061;
	for(i = 0; i < 10; i++)
		NOP;
	 SPCR2  |= 0x0080; //FRST=1
	for(i = 0; i < 6; i++)
		NOP;
		
}*/
//===========================================================================
// No more.
//===========================================================================