📄 dsp281x_pievectint.c
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/*****************************************************************************/
/* */
/* File: DSP281x_PieVectInt.c */
/* */
/* Title: PIE INTERUPT */
/* Description: This file is a sample F2812 PieInterruptVector file that */
/* can be used for initializing the pie interrupt vectors. */
/* Use it as a guideline; you may want to add your needed */
/* interrupts at the corresponding position and add their */
/* service functions. All service functions of interrupts */
/* will be added in the file. */
/*****************************************************************************/
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|=======|===============================================
// 1.00| 12 Mar 2004 | Z.Y.Y | First Version V1.0
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|=======|===============================================
// 1.00| 30 June 2004 | Y.Z.Y | Second Version V2.0
//###########################################################################
#include "DSP281x_PieVect.h"
#include "F2812reg.h"
#pragma DATA_SECTION(PieVectTable,"PieVectTable");
struct PIE_VECT_TABLE PieVectTable;
const struct PIE_VECT_TABLE PieVectTableInit = /* Interrupt vector table (doesn't include RESET) */
{
UnusedIsr,
UnusedIsr, /* INT1 - Maskable int 1 */
UnusedIsr, /* INT2 - Maskable int 2 */
UnusedIsr, /* INT3 - Maskable int 3 */
UnusedIsr, /* INT4 - Maskable int 4 */
UnusedIsr, /* INT5 - Maskable int 5 */
UnusedIsr, /* INT6 - Maskable int 6 */
UnusedIsr, /* INT7 - Maskable int 7 */
UnusedIsr, /* INT8 - Maskable int 8 */
UnusedIsr, /* INT9 - Maskable int 9 */
UnusedIsr, /* INT10 - Maskable int 10 */
UnusedIsr, /* INT11 - Maskable int 11 */
UnusedIsr, /* INT12 - Maskable int 12 */
UnusedIsr, /* INT13 - Maskable int 13, timer 1 */
UnusedIsr, /* INT14 - Maskable int 14, timer 2 */
UnusedIsr, /* DLOGINT- Maskable data-logging int */
UnusedIsr, /* RTOSINT- Maskable real-time OS int */
UnusedIsr, /* Reserved */
UnusedIsr, /* NMI - Nonmaskable interrupt */
UnusedIsr, /* ILLEGAL- Illegal instruction trap */
UnusedIsr, /* USER1 - User-defined sw int/trap */
UnusedIsr, /* USER2 - User-defined sw int/trap */
UnusedIsr, /* USER3 - User-defined sw int/trap */
UnusedIsr, /* USER4 - User-defined sw int/trap */
UnusedIsr, /* USER5 - User-defined sw int/trap */
UnusedIsr, /* USER6 - User-defined sw int/trap */
UnusedIsr, /* USER7 - User-defined sw int/trap */
UnusedIsr, /* USER8 - User-defined sw int/trap */
UnusedIsr, /* USER9 - User-defined sw int/trap */
UnusedIsr, /* USER10 - User-defined sw int/trap */
UnusedIsr, /* USER11 - User-defined sw int/trap */
UnusedIsr, /* USER12 - User-defined sw int/trap */
UnusedIsr, /* PIE int 1.1 */
UnusedIsr, /* PIE int 1.2 */
UnusedIsr, /* PIE int 1.3 */
Xint1Isr, /* PIE int 1.4 */
Xint2Isr, /* PIE int 1.5 */
AdcIntIsr, /* PIE int 1.6 */
CpuTimer0Isr, /* PIE int 1.7, TINT0 (Timer 0) */
UnusedIsr, /* PIE int 1.8 */
UnusedIsr, //PIE2
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr, //PIE3
UnusedIsr,
UnusedIsr,
UnusedIsr,
EvCap1Isr,
EvCap2Isr,
EvCap3Isr,
UnusedIsr,
UnusedIsr, //PIE4
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
EvTimer4Isr, //PIE5
UnusedIsr,
UnusedIsr,
UnusedIsr,
EvCap4Isr,
EvCap5Isr,
EvCap6Isr,
UnusedIsr,
SpiRxIsr, //PIE6 int 1.1 SPI RX INT
SpiTxIsr, //PIE6 int 1.2 SPI TX INT
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr, //PIE7
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr, //PIE8
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
UnusedIsr,
//PIE9
SciaRxIsr, /* PIE int 1.1, SCIA RX INT */
SciaTxIsr, /* PIE int 1.2, SCIA TX INT */
ScibRxIsr, /* PIE int 1.3, SCIB RX INT */
ScibTxIsr, /* PIE int 1.4, SCIB TX INT */
Ecan0Isr, /* PIE int 1.5, ECAN0 INT */
Ecan1Isr, /* PIE int 1.6 ECAN1 INT */
UnusedIsr, /* PIE int 1.7 */
UnusedIsr, /* PIE int 1.8 */
};
/*-------------------PIE Interrupts Routine Zone Start----------------------------*/
interrupt void UnusedIsr(void)
{
return;
}
interrupt void Xint1Isr(void)
{
// PerformXint1();
PIEACK |= PIEACK_GROUP1; /* Acknowledge PIE group 1 int */
return;
}
interrupt void Xint2Isr(void)
{
// PerformXint2();
PIEACK |= PIEACK_GROUP1; /* Acknowledge PIE group 1 int */
return;
}
interrupt void AdcIntIsr(void)
{
// PerformAdc();
PIEACK |= PIEACK_GROUP1; /* Acknowledge PIE group 1 int */
return;
}
interrupt void CpuTimer0Isr(void)
{
// PerformCpuTimer0();
PIEACK |= PIEACK_GROUP1; /* Acknowledge PIE group 1 int */
return;
}
interrupt void EvTimer1Isr(void)
{
// PerformEvTimer1();
EVBIFRA = BIT7;
PIEACK |= PIEACK_GROUP2; /* Acknowledge PIE group 2 int */
return;
}
interrupt void EvCap1Isr(void)
{
// PerformEvCap1();
CAPFIFOA &= 0xFCFF;
EVAIFRC |= BIT0;
PIEACK |= PIEACK_GROUP3; /* Acknowledge PIE group 3 int */
EINT;
return;
}
interrupt void EvCap2Isr(void)
{
// PerformEvCap2();
CAPFIFOA &= 0xF3FF;
EVAIFRC |= BIT1;
PIEACK |= PIEACK_GROUP3; /* Acknowledge PIE group 3 int */
EINT;
return;
}
interrupt void EvCap3Isr(void)
{
// PerformEvCap3();
PIEACK |= PIEACK_GROUP3; /* Acknowledge PIE group 3 int */
return;
}
interrupt void EvTimer4Isr(void)
{
EINT;
EVBIFRB = BIT0;
PIEACK |= PIEACK_GROUP5; /* Acknowledge PIE group 4 int */
// PerformEvTimer4();
return;
}
interrupt void EvCap4Isr(void)
{
// PerformEvCap4();
CAPFIFOB &= 0xFCFF;
EVBIFRC |= BIT0;
PIEACK |= PIEACK_GROUP5; /* Acknowledge PIE group 5 int */
EINT;
return;
}
interrupt void EvCap5Isr(void)
{
// PerformEvCap5();
CAPFIFOB &= 0xF3FF;
EVBIFRC |= BIT1;
PIEACK |= PIEACK_GROUP5; /* Acknowledge PIE group 5 int */
EINT;
return;
}
interrupt void EvCap6Isr(void)
{
// PerformEvCap6();
PIEACK |= PIEACK_GROUP5; /* Acknowledge PIE group 5 int */
return;
}
interrupt void SpiRxIsr(void)
{
// PerformSpiRx();
SPIFFRX |= BIT14; //clear overflow flag
SPIFFRX |= BIT6; //clear interrupt flag
PIEACK |= PIEACK_GROUP6; /* Acknowledge PIE group 6 int */
return;
}
interrupt void SpiTxIsr(void)
{
// PerformSpiTx();
SPIFFTX |= BIT6; // Clear Interrupt flag
PIEACK |= PIEACK_GROUP6; /* Acknowledge PIE group 6 int */
return;
}
interrupt void SciaRxIsr(void)
{
IER |= (M_INT3 | M_INT5);
PIEACK |= PIEACK_GROUP9; /* Acknowledge PIE group 9 int */
// PerformSciaRx();
return;
}
interrupt void SciaTxIsr(void)
{
IER |= (M_INT3 | M_INT5);
PIEACK |= PIEACK_GROUP9; /* Acknowledge PIE group 9 int */
EINT;
// PerformSciaTx();
return;
}
interrupt void ScibRxIsr(void)
{
IER |= (M_INT3 | M_INT5);
PIEACK |= PIEACK_GROUP9; /* Acknowledge PIE group 9 int */
// PerformScibRx();
return;
}
interrupt void ScibTxIsr(void)
{
IER |= (M_INT3 | M_INT5);
PIEACK |= PIEACK_GROUP9; /* Acknowledge PIE group 9 int */
// PerformScibTx();
return;
}
interrupt void Ecan0Isr(void)
{
PIEACK |= PIEACK_GROUP9; /* Acknowledge PIE group 9 int */
// PerformEcan0();
return;
}
interrupt void Ecan1Isr(void)
{
// PerformEcan1();
PIEACK |= PIEACK_GROUP9; /* Acknowledge PIE group 9 int */
IER |= 0x0100; // Enable INT 9
EINT;
return;
}
/*-------------------PIE Interrupts Routine Zone End------------------------------*/
//===========================================================================
// InitPieCtrl:
// This function initializes the PIE control registers to a known state.
//===========================================================================
void InitPieCtrl(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Disable the PIE
PIECTRL &= 0;
// Clear all PIEIER registers:
PIEIER1 = 0;
PIEIER2 = 0;
PIEIER3 = 0;
PIEIER4 = 0;
PIEIER5 = 0;
PIEIER6 = 0;
PIEIER7 = 0;
PIEIER8 = 0;
PIEIER9 = 0;
PIEIER10 = 0;
PIEIER11 = 0;
PIEIER12 = 0;
// Clear all PIEIFR registers:
PIEIFR1 = 0;
PIEIFR2 = 0;
PIEIFR3 = 0;
PIEIFR4 = 0;
PIEIFR5 = 0;
PIEIFR6 = 0;
PIEIFR7 = 0;
PIEIFR8 = 0;
PIEIFR9 = 0;
PIEIFR10 = 0;
PIEIFR11 = 0;
PIEIFR12 = 0;
}
//===========================================================================
// EnableInterrupts:
// This function enables the PIE module and CPU interrupts
//===========================================================================
void EnableInterrupts()
{
// Enable the PIE
PIECTRL |= 1;
// Enables PIE to drive a pulse into the CPU
PIEACK = 0xFFFF;
// Enable the PIE Vector Table
PIECTRL |= 1;
PIEIER1 = 0x78; // Enable XINT1,2 TINT0, ADCINT
// PIEIER2 = 0x08; // Enable T1PINT
PIEIER3 = 0x70; // Enable CAPINT1,2,3
// PIEIER4 = 0x08; // Enable T3PINT
PIEIER5 = 0x71; // Enable CAPINT4,5,6 and T4PINT
PIEIER6 = 0x03; // Enable SPI RX, TX INT
PIEIER9 = 0x3F; // Enable Ecan0 and Ecan1; SCIA and SCIB RI,TI
IER = 0xFFFF;
asm(" mov *SP++, #0x013F ; Want to enable INT1,2,3,4,5,6,9 DBGIER.");
asm(" pop DBGIER ; ...register");
// Enable Interrupts at the CPU level
EINT;
ERTM;
}
//===========================================================================
// InitPieVectTable:
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//===========================================================================
void InitPieVectTable(void)
{
int16 i;
uint32 *Source = (void *) &PieVectTableInit;
uint32 *Dest = (void *) &PieVectTable;
EALLOW; // Enable accesses to protected registers
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS; // Disable accesses to protected registers
// Enable the PIE
PIECTRL |= 1;
}
/*EOF*/
//===========================================================================
// No more.
//===========================================================================
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