regs240x.h

使用TI DSP 2407A 进行开发的源代码

#define T1PER              *(Val_T1PER	)    /*   GP Timer 1 period register.         */
#define T1CON              *(Val_T1CON	)    /*   GP Timer 1 control register.        */
#define T2CNT              *(Val_T2CNT	)    /*   GP Timer 2 counter register.        */
#define T2CMPR             *(Val_T2CMPR	)    /*   GP Timer 2 compare register.        */
#define T2PR               *(Val_T2PR	)    /*   GP Timer 2 period register.         */
#define T2PER              *(Val_T2PER	)    /*   GP Timer 2 period register.         */
#define T2CON              *(Val_T2CON	)    /*   GP Timer 2 control register.        */
#define COMCONA            *(Val_COMCONA	)    /*   Compare control register A.         */
#define ACTRA              *(Val_ACTRA	)    /*   Full compare action control register*/
#define DBTCONA            *(Val_DBTCONA	)    /*   Dead-band timer control register A. */
#define CMPR1              *(Val_CMPR1	)    /*   Full compare unit compare register1 */
#define CMPR2              *(Val_CMPR2	)    /*   Full compare unit compare register2 */
#define CMPR3              *(Val_CMPR3	)    /*   Full compare unit compare register3 */
#define CAPCONA            *(Val_CAPCONA	)    /*   Capture control register A.         */
#define CAPFIFOA           *(Val_CAPFIFOA	)    /*   Capture FIFO status register A.     */
#define CAP1FIFO           *(Val_CAP1FIFO	)    /*   Capture Channel 1 FIFO Top          */
#define CAP2FIFO           *(Val_CAP2FIFO	)    /*   Capture Channel 2 FIFO Top          */
#define CAP3FIFO           *(Val_CAP3FIFO	)    /*   Capture Channel 3 FIFO Top          */
#define CAP1FBOT           *(Val_CAP1FBOT	)    /*   Bottom reg. pf capture FIFO stack 1 */
#define CAP2FBOT           *(Val_CAP2FBOT	)    /*   Bottom reg. pf capture FIFO stack 2 */
#define CAP3FBOT           *(Val_CAP3FBOT	)    /*   Bottom reg. pf capture FIFO stack 3 */
#define EVAIMRA            *(Val_EVAIMRA	)    /*   Group A Interrupt Mask Register A   */
#define EVAIMRB            *(Val_EVAIMRB	)    /*   Group B Interrupt Mask Register A   */
#define EVAIMRC            *(Val_EVAIMRC	)    /*   Group C Interrupt Mask Register A   */
#define EVAIFRA            *(Val_EVAIFRA	)    /*   Group A Interrupt Flag Register A   */
#define EVAIFRB            *(Val_EVAIFRB	)    /*   Group B Interrupt Flag Register A   */
#define EVAIFRC            *(Val_EVAIFRC	)    /*   Group C Interrupt Flag Register A   */
#define GPTCONB            *(Val_GPTCONB	)    /*   GP Timer control register B .       */
#define T3CNT              *(Val_T3CNT	)    /*   GP Timer 3 counter register.        */
#define T3CMPR             *(Val_T3CMPR	)    /*   GP Timer 3 compare register.        */
#define T3PR               *(Val_T3PR	)    /*   GP Timer 3 period register.         */
#define T3PER              *(Val_T3PER	)    /*   GP Timer 3 period register.         */
#define T3CON              *(Val_T3CON	)    /*   GP Timer 3 control register.        */
#define T4CNT              *(Val_T4CNT	)    /*   GP Timer 4 counter register.        */
#define T4CMPR             *(Val_T4CMPR	)    /*   GP Timer 4 compare register.        */
#define T4PR               *(Val_T4PR	)    /*   GP Timer 4 period register.         */
#define T4PER              *(Val_T4PER	)    /*   GP Timer 4 period register.         */
#define T4CON              *(Val_T4CON	)    /*   GP Timer 4 control register.        */
#define COMCONB            *(Val_COMCONB	)    /*   Compare control register B.         */
#define ACTRB              *(Val_ACTRB	)    /*   Full compare action control register*/
#define DBTCONB            *(Val_DBTCONB	)    /*   Dead-band timer control register B. */
#define CMPR4              *(Val_CMPR4	)    /*   Full compare unit compare register1 */
#define CMPR5              *(Val_CMPR5	)    /*   Full compare unit compare register2 */
#define CMPR6              *(Val_CMPR6	)    /*   Full compare unit compare register3 */
#define CAPCONB            *(Val_CAPCONB	)    /*   Capture control register B.         */
#define CAPFIFOB           *(Val_CAPFIFOB	)    /*   Capture FIFO status register B.     */
#define CAP4FIFO           *(Val_CAP4FIFO	)    /*   Capture Channel 1 FIFO Top B        */
#define CAP5FIFO           *(Val_CAP5FIFO	)    /*   Capture Channel 2 FIFO Top B        */
#define CAP6FIFO           *(Val_CAP6FIFO	)    /*   Capture Channel 3 FIFO Top B        */
#define CAP4FBOT           *(Val_CAP4FBOT	)    /*   Bottom reg. pf capture FIFO stack 1 */
#define CAP5FBOT           *(Val_CAP5FBOT	)    /*   Bottom reg. pf capture FIFO stack 2 */
#define CAP6FBOT           *(Val_CAP6FBOT	)    /*   Bottom reg. pf capture FIFO stack 3 */
#define EVBIMRA            *(Val_EVBIMRA	)    /*   Group A Interrupt Mask Register B   */
#define EVBIMRB            *(Val_EVBIMRB	)    /*   Group B Interrupt Mask Register B   */
#define EVBIMRC            *(Val_EVBIMRC	)    /*   Group C Interrupt Mask Register B   */
#define EVBIFRA            *(Val_EVBIFRA	)    /*   Group A Interrupt Flag Register B   */
#define EVBIFRB            *(Val_EVBIFRB	)    /*   Group B Interrupt Flag Register B   */
#define EVBIFRC            *(Val_EVBIFRC	)    /*   Group C Interrupt Flag Register B   */
#define CANMDER            *(Val_CANMDER	)    /*   CAN Mailbox Direction/Enable reg    */
#define CANTCR             *(Val_CANTCR	)    /*   CAN Transmission Control Reg        */
#define CANRCR             *(Val_CANRCR	)    /*   CAN Recieve COntrol Reg             */
#define CANMCR             *(Val_CANMCR	)    /*   CAN Master Control Reg              */
#define CANBCR2            *(Val_CANBCR2	)    /*   CAN Bit COnfig Reg 2                */
#define CANBCR1            *(Val_CANBCR1	)    /*   CAN Bit Config Reg 1                */
#define CANESR             *(Val_CANESR	)    /*   CAN Error Status Reg                */
#define CANGSR             *(Val_CANGSR	)    /*   CAN Global Status Reg               */
#define CANCEC             *(Val_CANCEC	)    /*   CAN Trans and Rcv Err counters      */
#define CANIFR             *(Val_CANIFR	)    /*   CAN Interrupt Flag Registers        */
#define CANIMR             *(Val_CANIMR	)    /*   CAN Interrupt Mask Registers        */
#define CANLAM0H           *(Val_CANLAM0H	)    /*   CAN Local Acceptance Mask MBx0/1    */
#define CANLAM0L           *(Val_CANLAM0L	)    /*   CAN Local Acceptance Mask MBx0/1    */
#define CANLAM1H           *(Val_CANLAM1H	)    /*   CAN Local Acceptance Mask MBx2/3    */
#define CANLAM1L           *(Val_CANLAM1L	)    /*   CAN Local Acceptance Mask MBx2/3    */
#define CANMSGID0L         *(Val_CANMSGID0L	)    /*   CAN Message ID for mailbox 0 (lower */
#define CANMSGID0H         *(Val_CANMSGID0H	)    /*   CAN Message ID for mailbox 0 (upper */
#define CANMSGCTRL0        *(Val_CANMSGCTRL0	)    /*   CAN RTR and DLC                     */
#define CANMBX0A           *(Val_CANMBX0A	)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMBX0B           *(Val_CANMBX0B	)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMBX0C           *(Val_CANMBX0C	)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMBX0D           *(Val_CANMBX0D	)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMSGID1L         *(Val_CANMSGID1L	)    /*   CAN Message ID for mailbox 1 (lower */
#define CANMSGID1H         *(Val_CANMSGID1H	)    /*   CAN Message ID for mailbox 1 (upper */
#define CANMSGCTRL1        *(Val_CANMSGCTRL1	)    /*   CAN RTR and DLC                     */
#define CANMBX1A           *(Val_CANMBX1A	)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMBX1B           *(Val_CANMBX1B	)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMBX1C           *(Val_CANMBX1C	)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMBX1D           *(Val_CANMBX1D	)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMSGID2L         *(Val_CANMSGID2L	)    /*   CAN Message ID for mailbox 2 (lower */
#define CANMSGID2H         *(Val_CANMSGID2H	)    /*   CAN Message ID for mailbox 2 (upper */
#define CANMSGCTRL2        *(Val_CANMSGCTRL2	)    /*   CAN RTR and DLC                     */
#define CANMBX2A           *(Val_CANMBX2A	)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMBX2B           *(Val_CANMBX2B	)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMBX2C           *(Val_CANMBX2C	)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMBX2D           *(Val_CANMBX2D	)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMSGID3L         *(Val_CANMSGID3L	)    /*   CAN Message ID for mailbox 3 (lower */
#define CANMSGID3H         *(Val_CANMSGID3H	)    /*   CAN Message ID for mailbox 3 (upper */
#define CANMSGCTRL3        *(Val_CANMSGCTRL3	)    /*   CAN RTR and DLC                     */
#define CANMBX3A           *(Val_CANMBX3A	)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMBX3B           *(Val_CANMBX3B	)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMBX3C           *(Val_CANMBX3C	)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMBX3D           *(Val_CANMBX3D	)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMSGID4L         *(Val_CANMSGID4L	)    /*   CAN Message ID for mailbox 4 (lower */
#define CANMSGID4H         *(Val_CANMSGID4H	)    /*   CAN Message ID for mailbox 4 (upper */
#define CANMSGCTRL4        *(Val_CANMSGCTRL4	)    /*   CAN RTR and DLC                     */
#define CANMBX4A           *(Val_CANMBX4A	)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMBX4B           *(Val_CANMBX4B	)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMBX4C           *(Val_CANMBX4C	)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMBX4D           *(Val_CANMBX4D	)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMSGID5L         *(Val_CANMSGID5L	)    /*   CAN Message ID for mailbox 5 (lower */
#define CANMSGID5H         *(Val_CANMSGID5H	)    /*   CAN Message ID for mailbox 5 (upper */
#define CANMSGCTRL5        *(Val_CANMSGCTRL5	)    /*   CAN RTR and DLC                     */
#define CANMBX5A           *(Val_CANMBX5A	)    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define CANMBX5B           *(Val_CANMBX5B	)    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define CANMBX5C           *(Val_CANMBX5C	)    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define CANMBX5D           *(Val_CANMBX5D	)    /*   CAN 2 of 8 bytes of Mailbox 5       */






/*--------------------------------------------------------------------------*/
/* I/O space mapped registers						    */
/*--------------------------------------------------------------------------*/
#define WSGR	portffff	
ioport unsigned portffff;       /* Wait-State Generator Control Reg */

/*#define FCMR	portff0f	/* Flash mode control register */
/*ioport unsigned portff0f;
ioport unsigned port0;
ioport unsigned port1;
ioport unsigned port2;
ioport unsigned port3;
ioport unsigned port4;  

#define DAC0	port0
#define DAC1	port1
#define DAC2	port2
#define DAC3	port3
#define DACL	port4*/

#endif /*__REGS240X_H__  */