regs240x.h

使用TI DSP 2407A 进行开发的源代码

#define  Val_CAP6FBOT           (volatile unsigned int *) 0x7527    /*   Bottom reg. pf capture FIFO stack 3 */
#define  Val_EVBIMRA            (volatile unsigned int *) 0x752C    /*   Group A Interrupt Mask Register B   */
#define  Val_EVBIMRB            (volatile unsigned int *) 0x752D    /*   Group B Interrupt Mask Register B   */
#define  Val_EVBIMRC            (volatile unsigned int *) 0x752E    /*   Group C Interrupt Mask Register B   */
#define  Val_EVBIFRA            (volatile unsigned int *) 0x752F    /*   Group A Interrupt Flag Register B   */
#define  Val_EVBIFRB            (volatile unsigned int *) 0x7530    /*   Group B Interrupt Flag Register B   */
#define  Val_EVBIFRC            (volatile unsigned int *) 0x7531    /*   Group C Interrupt Flag Register B   */
#define  Val_CANMDER            (volatile unsigned int *) 0x7100    /*   CAN Mailbox Direction/Enable reg    */
#define  Val_CANTCR             (volatile unsigned int *) 0x7101    /*   CAN Transmission Control Reg        */
#define  Val_CANRCR             (volatile unsigned int *) 0x7102    /*   CAN Recieve COntrol Reg             */
#define  Val_CANMCR             (volatile unsigned int *) 0x7103    /*   CAN Master Control Reg              */
#define  Val_CANBCR2            (volatile unsigned int *) 0x7104    /*   CAN Bit COnfig Reg 2                */
#define  Val_CANBCR1            (volatile unsigned int *) 0x7105    /*   CAN Bit Config Reg 1                */
#define  Val_CANESR             (volatile unsigned int *) 0x7106    /*   CAN Error Status Reg                */
#define  Val_CANGSR             (volatile unsigned int *) 0x7107    /*   CAN Global Status Reg               */
#define  Val_CANCEC             (volatile unsigned int *) 0x7108    /*   CAN Trans and Rcv Err counters      */
#define  Val_CANIFR             (volatile unsigned int *) 0x7109    /*   CAN Interrupt Flag Registers        */
#define  Val_CANIMR             (volatile unsigned int *) 0x710a    /*   CAN Interrupt Mask Registers        */
#define  Val_CANLAM0H           (volatile unsigned int *) 0x710b    /*   CAN Local Acceptance Mask MBx0/1    */
#define  Val_CANLAM0L           (volatile unsigned int *) 0x710c    /*   CAN Local Acceptance Mask MBx0/1    */
#define  Val_CANLAM1H           (volatile unsigned int *) 0x710d    /*   CAN Local Acceptance Mask MBx2/3    */
#define  Val_CANLAM1L           (volatile unsigned int *) 0x710e    /*   CAN Local Acceptance Mask MBx2/3    */
#define  Val_CANMSGID0L         (volatile unsigned int *) 0x7200    /*   CAN Message ID for mailbox 0 (lower */
#define  Val_CANMSGID0H         (volatile unsigned int *) 0x7201    /*   CAN Message ID for mailbox 0 (upper */
#define  Val_CANMSGCTRL0        (volatile unsigned int *) 0x7202    /*   CAN RTR and DLC                     */
#define  Val_CANMBX0A           (volatile unsigned int *) 0x7204    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define  Val_CANMBX0B           (volatile unsigned int *) 0x7205    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define  Val_CANMBX0C           (volatile unsigned int *) 0x7206    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define  Val_CANMBX0D           (volatile unsigned int *) 0x7207    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define  Val_CANMSGID1L         (volatile unsigned int *) 0x7208    /*   CAN Message ID for mailbox 1 (lower */
#define  Val_CANMSGID1H         (volatile unsigned int *) 0x7209    /*   CAN Message ID for mailbox 1 (upper */
#define  Val_CANMSGCTRL1        (volatile unsigned int *) 0x720A    /*   CAN RTR and DLC                     */
#define  Val_CANMBX1A           (volatile unsigned int *) 0x720C    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define  Val_CANMBX1B           (volatile unsigned int *) 0x720D    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define  Val_CANMBX1C           (volatile unsigned int *) 0x720E    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define  Val_CANMBX1D           (volatile unsigned int *) 0x720F    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define  Val_CANMSGID2L         (volatile unsigned int *) 0x7210    /*   CAN Message ID for mailbox 2 (lower */
#define  Val_CANMSGID2H         (volatile unsigned int *) 0x7211    /*   CAN Message ID for mailbox 2 (upper */
#define  Val_CANMSGCTRL2        (volatile unsigned int *) 0x7212    /*   CAN RTR and DLC                     */
#define  Val_CANMBX2A           (volatile unsigned int *) 0x7214    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define  Val_CANMBX2B           (volatile unsigned int *) 0x7215    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define  Val_CANMBX2C           (volatile unsigned int *) 0x7216    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define  Val_CANMBX2D           (volatile unsigned int *) 0x7217    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define  Val_CANMSGID3L         (volatile unsigned int *) 0x7218    /*   CAN Message ID for mailbox 3 (lower */
#define  Val_CANMSGID3H         (volatile unsigned int *) 0x7219    /*   CAN Message ID for mailbox 3 (upper */
#define  Val_CANMSGCTRL3        (volatile unsigned int *) 0x721A    /*   CAN RTR and DLC                     */
#define  Val_CANMBX3A           (volatile unsigned int *) 0x721C    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define  Val_CANMBX3B           (volatile unsigned int *) 0x721D    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define  Val_CANMBX3C           (volatile unsigned int *) 0x721E    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define  Val_CANMBX3D           (volatile unsigned int *) 0x721F    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define  Val_CANMSGID4L         (volatile unsigned int *) 0x7220    /*   CAN Message ID for mailbox 4 (lower */
#define  Val_CANMSGID4H         (volatile unsigned int *) 0x7221    /*   CAN Message ID for mailbox 4 (upper */
#define  Val_CANMSGCTRL4        (volatile unsigned int *) 0x7222    /*   CAN RTR and DLC                     */
#define  Val_CANMBX4A           (volatile unsigned int *) 0x7224    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define  Val_CANMBX4B           (volatile unsigned int *) 0x7225    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define  Val_CANMBX4C           (volatile unsigned int *) 0x7226    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define  Val_CANMBX4D           (volatile unsigned int *) 0x7227    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define  Val_CANMSGID5L         (volatile unsigned int *) 0x7228    /*   CAN Message ID for mailbox 5 (lower */
#define  Val_CANMSGID5H         (volatile unsigned int *) 0x7229    /*   CAN Message ID for mailbox 5 (upper */
#define  Val_CANMSGCTRL5        (volatile unsigned int *) 0x722A    /*   CAN RTR and DLC                     */
#define  Val_CANMBX5A           (volatile unsigned int *) 0x722C    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define  Val_CANMBX5B           (volatile unsigned int *) 0x722D    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define  Val_CANMBX5C           (volatile unsigned int *) 0x722E    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define  Val_CANMBX5D           (volatile unsigned int *) 0x722F   



#define IMR                *(Val_IMR	)    /*   Interrupt Mask Register             */
#define IFR                *(Val_IFR	)    /*   Interrupt Flag Register             */
#define SCSR1              *(Val_SCSR1	)    /*   System Control &  Status Reg. 1     */
#define SCSR2              *(Val_SCSR2	)    /*   System Control &  Status Reg. 2     */
#define DINR               *(Val_DINR	)    /*   Device Identification Register.     */
#define PIVR               *(Val_PIVR	)    /*   Peripheral Interrupt Vector Reg.    */
#define PIRQR0             *(Val_PIRQR0	)    /*   Periph Interrupt Request Reg 0.     */
#define PIRQR1             *(Val_PIRQR1	)    /*   Periph Interrupt Request Reg 1.     */
#define PIRQR2             *(Val_PIRQR2	)    /*   Periph Interrupt Request Reg 2.     */
#define PIACKR0            *(Val_PIACKR0	)    /*   Periph Interrupt Acknowledge Reg 0. */
#define PIACKR1            *(Val_PIACKR1	)    /*   Periph Interrupt Acknowledge Reg 1. */
#define PIACKR2            *(Val_PIACKR2	)    /*   Periph Interrupt Acknowledge Reg 2. */
#define XINT1CR            *(Val_XINT1CR	)    /*   Ext. interrupt 1 config reg for X241*/
#define XINT2CR            *(Val_XINT2CR	)    /*   External interrupt 2 config. X241/2/*/
#define MCRA               *(Val_MCRA	)    /*   Output Control Reg A                */
#define OCRA               *(Val_OCRA	)    /*   Output Control Reg A                */
#define MCRB               *(Val_MCRB	)    /*   Output Control Reg B                */
#define OCRB               *(Val_OCRB	)    /*   Output Control Reg B                */
#define MCRC               *(Val_MCRC	)    /*   Output Control Reg C                */
#define ISRA               *(Val_ISRA	)    /*   Input Status Reg A x240x only       */
#define ISRB               *(Val_ISRB	)    /*   Input Status Reg B x240x only       */
#define PADATDIR           *(Val_PADATDIR	)    /*   I/O port A Data & Direction reg.    */
#define PBDATDIR           *(Val_PBDATDIR	)    /*   I/O port B Data & Direction reg.    */
#define PCDATDIR           *(Val_PCDATDIR	)    /*   I/O port C Data & Direction reg.    */
#define PDDATDIR           *(Val_PDDATDIR	)    /*   I/O port D Data & Direction reg.    */
#define PEDATDIR           *(Val_PEDATDIR	)    /*   I/O port E Data & Direction reg.    */
#define PFDATDIR           *(Val_PFDATDIR	)    /*   I/O port F Data & Direction reg.    */
#define WDCNTR             *(Val_WDCNTR	)    /*   WD Counter reg                      */
#define WDKEY              *(Val_WDKEY	)    /*   WD Key reg                          */
#define WDCR               *(Val_WDCR	)    /*   WD Control reg                      */
#define ADCTRL1            *(Val_ADCTRL1	)    /*   ADC Control Reg1                    */
#define ADCTRL2            *(Val_ADCTRL2	)    /*   ADC Control Reg2                    */
#define MAXCONV            *(Val_MAXCONV	)    /*   Maximum conversion channels register*/
#define CHSELSEQ1          *(Val_CHSELSEQ1	)    /*   Channel select Sequencing control re*/
#define CHSELSEQ2          *(Val_CHSELSEQ2	)    /*   Channel select Sequencing control re*/
#define CHSELSEQ3          *(Val_CHSELSEQ3	)    /*   Channel select Sequencing control re*/
#define CHSELSEQ4          *(Val_CHSELSEQ4	)    /*   Channel select Sequencing control re*/
#define AUTO_SEQ_SR        *(Val_AUTO_SEQ_SR	)    /*   Auto-sequence status register       */
#define RESULT0            *(Val_RESULT0	)    /*   Conversion result buffer register 0 */
#define RESULT1            *(Val_RESULT1	)    /*   Conversion result buffer register 1 */
#define RESULT2            *(Val_RESULT2	)    /*   Conversion result buffer register 2 */
#define RESULT3            *(Val_RESULT3	)    /*   Conversion result buffer register 3 */
#define RESULT4            *(Val_RESULT4	)    /*   Conversion result buffer register 4 */
#define RESULT5            *(Val_RESULT5	)    /*   Conversion result buffer register 5 */
#define RESULT6            *(Val_RESULT6	)    /*   Conversion result buffer register 6 */
#define RESULT7            *(Val_RESULT7	)    /*   Conversion result buffer register 7 */
#define RESULT8            *(Val_RESULT8	)    /*   Conversion result buffer register 8 */
#define RESULT9            *(Val_RESULT9	)    /*   Conversion result buffer register 9 */
#define RESULT10           *(Val_RESULT10	)    /*   Conversion result buffer register 10*/
#define RESULT11           *(Val_RESULT11	)    /*   Conversion result buffer register 11*/
#define RESULT12           *(Val_RESULT12	)    /*   Conversion result buffer register 12*/
#define RESULT13           *(Val_RESULT13	)    /*   Conversion result buffer register 13*/
#define RESULT14           *(Val_RESULT14	)    /*   Conversion result buffer register 14*/
#define RESULT15           *(Val_RESULT15	)    /*   Conversion result buffer register 15*/
#define CALIBRATION        *(Val_CALIBRATION	)    /*   Calib result, used to correct subseq*/
#define SPICCR             *(Val_SPICCR	)    /*   SPI Config Control Reg              */
#define SPICTL             *(Val_SPICTL	)    /*   SPI Operation Control Reg           */
#define SPISTS             *(Val_SPISTS	)    /*   SPI Status Reg                      */
#define SPIBRR             *(Val_SPIBRR	)    /*   SPI Baud rate control reg           */
#define SPIRXEMU           *(Val_SPIRXEMU	)    /*   SPI Emulation buffer reg            */
#define SPIRXBUF           *(Val_SPIRXBUF	)    /*   SPI Serial receive buffer reg       */
#define SPITXBUF           *(Val_SPITXBUF	)    /*   SPI Serial transmit buffer reg      */
#define SPIDAT             *(Val_SPIDAT	)    /*   SPI Serial data reg                 */
#define SPIPRI             *(Val_SPIPRI	)    /*   SPI Priority control reg            */
#define SCICCR             *(Val_SCICCR	)    /*   SCI Communication control reg       */
#define SCICTL1            *(Val_SCICTL1	)    /*   SCI Control reg1                    */
#define SCIHBAUD           *(Val_SCIHBAUD	)    /*   SCI Baud Rate MSbyte reg            */
#define SCILBAUD           *(Val_SCILBAUD	)    /*   SCI Baud Rate LSbyte reg            */
#define SCICTL2            *(Val_SCICTL2	)    /*   SCI Control reg2                    */
#define SCIRXST            *(Val_SCIRXST	)    /*   SCI Receiver Status reg             */
#define SCIRXEMU           *(Val_SCIRXEMU	)    /*   SCI Emulation Data Buffer reg       */
#define SCIRXBUF           *(Val_SCIRXBUF	)    /*   SCI Receiver Data buffer reg        */
#define SCITXBUF           *(Val_SCITXBUF	)    /*   SCI Transmit Data buffer reg        */
#define SCIPRI             *(Val_SCIPRI	)    /*   SCI Priority control reg            */
#define GPTCONA            *(Val_GPTCONA	)    /*   GP Timer control register A .       */
#define T1CNT              *(Val_T1CNT	)    /*   GP Timer 1 counter register.        */
#define T1CMPR             *(Val_T1CMPR	)    /*   GP Timer 1 compare register.        */
#define T1PR               *(Val_T1PR	)    /*   GP Timer 1 period register.         */