📄 regs240x.h
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/* ==================================================================================
File name: regs240x.h
Originator: Digital Control Systems Group
Texas Instruments
Description: F240x register definitions.
=====================================================================================
History:
-------------------------------------------------------------------------------------
9-15-2000 Release Rev 1.0
---------------------------------------------------------------------------------- */
#ifndef __REGS240X_H__
#define __REGS240X_H__
#define Val_IMR (volatile unsigned int *) 0x0004 /* Interrupt Mask Register */
#define Val_IFR (volatile unsigned int *) 0x0006 /* Interrupt Flag Register */
#define Val_SCSR1 (volatile unsigned int *) 0x7018 /* System Control & Status Reg. 1 */
#define Val_SCSR2 (volatile unsigned int *) 0x7019 /* System Control & Status Reg. 2 */
#define Val_DINR (volatile unsigned int *) 0x701C /* Device Identification Register. */
#define Val_PIVR (volatile unsigned int *) 0x701E /* Peripheral Interrupt Vector Reg. */
#define Val_PIRQR0 (volatile unsigned int *) 0x7010 /* Periph Interrupt Request Reg 0. */
#define Val_PIRQR1 (volatile unsigned int *) 0x7011 /* Periph Interrupt Request Reg 1. */
#define Val_PIRQR2 (volatile unsigned int *) 0x7012 /* Periph Interrupt Request Reg 2. */
#define Val_PIACKR0 (volatile unsigned int *) 0x7014 /* Periph Interrupt Acknowledge Reg 0. */
#define Val_PIACKR1 (volatile unsigned int *) 0x7015 /* Periph Interrupt Acknowledge Reg 1. */
#define Val_PIACKR2 (volatile unsigned int *) 0x7016 /* Periph Interrupt Acknowledge Reg 2. */
#define Val_XINT1CR (volatile unsigned int *) 0x7070 /* Ext. interrupt 1 config reg for X241*/
#define Val_XINT2CR (volatile unsigned int *) 0x7071 /* External interrupt 2 config. X241/2/*/
#define Val_MCRA (volatile unsigned int *) 0x7090 /* Output Control Reg A */
#define Val_OCRA (volatile unsigned int *) 0x7090 /* Output Control Reg A */
#define Val_MCRB (volatile unsigned int *) 0x7092 /* Output Control Reg B */
#define Val_OCRB (volatile unsigned int *) 0x7092 /* Output Control Reg B */
#define Val_MCRC (volatile unsigned int *) 0x7094 /* Output Control Reg C */
#define Val_ISRA (volatile unsigned int *) 0x7094 /* Input Status Reg A x24(volatile unsigned int *) 0x only */
#define Val_ISRB (volatile unsigned int *) 0x7096 /* Input Status Reg B x24(volatile unsigned int *) 0x only */
#define Val_PADATDIR (volatile unsigned int *) 0x7098 /* I/O port A Data & Direction reg. */
#define Val_PBDATDIR (volatile unsigned int *) 0x709A /* I/O port B Data & Direction reg. */
#define Val_PCDATDIR (volatile unsigned int *) 0x709C /* I/O port C Data & Direction reg. */
#define Val_PDDATDIR (volatile unsigned int *) 0x709E /* I/O port D Data & Direction reg. */
#define Val_PEDATDIR (volatile unsigned int *) 0x7095 /* I/O port E Data & Direction reg. */
#define Val_PFDATDIR (volatile unsigned int *) 0x7096 /* I/O port F Data & Direction reg. */
#define Val_WDCNTR (volatile unsigned int *) 0x7023 /* WD Counter reg */
#define Val_WDKEY (volatile unsigned int *) 0x7025 /* WD Key reg */
#define Val_WDCR (volatile unsigned int *) 0x7029 /* WD Control reg */
#define Val_ADCTRL1 (volatile unsigned int *) 0x70A0 /* ADC Control Reg1 */
#define Val_ADCTRL2 (volatile unsigned int *) 0x70A1 /* ADC Control Reg2 */
#define Val_MAXCONV (volatile unsigned int *) 0x70A2 /* Maximum conversion channels register*/
#define Val_CHSELSEQ1 (volatile unsigned int *) 0x70A3 /* Channel select Sequencing control re*/
#define Val_CHSELSEQ2 (volatile unsigned int *) 0x70A4 /* Channel select Sequencing control re*/
#define Val_CHSELSEQ3 (volatile unsigned int *) 0x70A5 /* Channel select Sequencing control re*/
#define Val_CHSELSEQ4 (volatile unsigned int *) 0x70A6 /* Channel select Sequencing control re*/
#define Val_AUTO_SEQ_SR (volatile unsigned int *) 0x70A7 /* Auto-sequence status register */
#define Val_RESULT0 (volatile unsigned int *) 0x70A8 /* Conversion result buffer register 0 */
#define Val_RESULT1 (volatile unsigned int *) 0x70A9 /* Conversion result buffer register 1 */
#define Val_RESULT2 (volatile unsigned int *) 0x70AA /* Conversion result buffer register 2 */
#define Val_RESULT3 (volatile unsigned int *) 0x70AB /* Conversion result buffer register 3 */
#define Val_RESULT4 (volatile unsigned int *) 0x70AC /* Conversion result buffer register 4 */
#define Val_RESULT5 (volatile unsigned int *) 0x70AD /* Conversion result buffer register 5 */
#define Val_RESULT6 (volatile unsigned int *) 0x70AE /* Conversion result buffer register 6 */
#define Val_RESULT7 (volatile unsigned int *) 0x70AF /* Conversion result buffer register 7 */
#define Val_RESULT8 (volatile unsigned int *) 0x70B0 /* Conversion result buffer register 8 */
#define Val_RESULT9 (volatile unsigned int *) 0x70B1 /* Conversion result buffer register 9 */
#define Val_RESULT10 (volatile unsigned int *) 0x70B2 /* Conversion result buffer register 10*/
#define Val_RESULT11 (volatile unsigned int *) 0x70B3 /* Conversion result buffer register 11*/
#define Val_RESULT12 (volatile unsigned int *) 0x70B4 /* Conversion result buffer register 12*/
#define Val_RESULT13 (volatile unsigned int *) 0x70B5 /* Conversion result buffer register 13*/
#define Val_RESULT14 (volatile unsigned int *) 0x70B6 /* Conversion result buffer register 14*/
#define Val_RESULT15 (volatile unsigned int *) 0x70B7 /* Conversion result buffer register 15*/
#define Val_CALIBRATION (volatile unsigned int *) 0x70B8 /* Calib result, used to correct subseq*/
#define Val_SPICCR (volatile unsigned int *) 0x7040 /* SPI Config Control Reg */
#define Val_SPICTL (volatile unsigned int *) 0x7041 /* SPI Operation Control Reg */
#define Val_SPISTS (volatile unsigned int *) 0x7042 /* SPI Status Reg */
#define Val_SPIBRR (volatile unsigned int *) 0x7044 /* SPI Baud rate control reg */
#define Val_SPIRXEMU (volatile unsigned int *) 0x7046 /* SPI Emulation buffer reg */
#define Val_SPIRXBUF (volatile unsigned int *) 0x7047 /* SPI Serial receive buffer reg */
#define Val_SPITXBUF (volatile unsigned int *) 0x7048 /* SPI Serial transmit buffer reg */
#define Val_SPIDAT (volatile unsigned int *) 0x7049 /* SPI Serial data reg */
#define Val_SPIPRI (volatile unsigned int *) 0x704F /* SPI Priority control reg */
#define Val_SCICCR (volatile unsigned int *) 0x7050 /* SCI Communication control reg */
#define Val_SCICTL1 (volatile unsigned int *) 0x7051 /* SCI Control reg1 */
#define Val_SCIHBAUD (volatile unsigned int *) 0x7052 /* SCI Baud Rate MSbyte reg */
#define Val_SCILBAUD (volatile unsigned int *) 0x7053 /* SCI Baud Rate LSbyte reg */
#define Val_SCICTL2 (volatile unsigned int *) 0x7054 /* SCI Control reg2 */
#define Val_SCIRXST (volatile unsigned int *) 0x7055 /* SCI Receiver Status reg */
#define Val_SCIRXEMU (volatile unsigned int *) 0x7056 /* SCI Emulation Data Buffer reg */
#define Val_SCIRXBUF (volatile unsigned int *) 0x7057 /* SCI Receiver Data buffer reg */
#define Val_SCITXBUF (volatile unsigned int *) 0x7059 /* SCI Transmit Data buffer reg */
#define Val_SCIPRI (volatile unsigned int *) 0x705F /* SCI Priority control reg */
#define Val_GPTCONA (volatile unsigned int *) 0x7400 /* GP Timer control register A . */
#define Val_T1CNT (volatile unsigned int *) 0x7401 /* GP Timer 1 counter register. */
#define Val_T1CMPR (volatile unsigned int *) 0x7402 /* GP Timer 1 compare register. */
#define Val_T1PR (volatile unsigned int *) 0x7403 /* GP Timer 1 period register. */
#define Val_T1PER (volatile unsigned int *) 0x7403 /* GP Timer 1 period register. */
#define Val_T1CON (volatile unsigned int *) 0x7404 /* GP Timer 1 control register. */
#define Val_T2CNT (volatile unsigned int *) 0x7405 /* GP Timer 2 counter register. */
#define Val_T2CMPR (volatile unsigned int *) 0x7406 /* GP Timer 2 compare register. */
#define Val_T2PR (volatile unsigned int *) 0x7407 /* GP Timer 2 period register. */
#define Val_T2PER (volatile unsigned int *) 0x7407 /* GP Timer 2 period register. */
#define Val_T2CON (volatile unsigned int *) 0x7408 /* GP Timer 2 control register. */
#define Val_COMCONA (volatile unsigned int *) 0x7411 /* Compare control register A. */
#define Val_ACTRA (volatile unsigned int *) 0x7413 /* Full compare action control register*/
#define Val_DBTCONA (volatile unsigned int *) 0x7415 /* Dead-band timer control register A. */
#define Val_CMPR1 (volatile unsigned int *) 0x7417 /* Full compare unit compare register1 */
#define Val_CMPR2 (volatile unsigned int *) 0x7418 /* Full compare unit compare register2 */
#define Val_CMPR3 (volatile unsigned int *) 0x7419 /* Full compare unit compare register3 */
#define Val_CAPCONA (volatile unsigned int *) 0x7420 /* Capture control register A. */
#define Val_CAPFIFOA (volatile unsigned int *) 0x7422 /* Capture FIFO status register A. */
#define Val_CAP1FIFO (volatile unsigned int *) 0x7423 /* Capture Channel 1 FIFO Top */
#define Val_CAP2FIFO (volatile unsigned int *) 0x7424 /* Capture Channel 2 FIFO Top */
#define Val_CAP3FIFO (volatile unsigned int *) 0x7425 /* Capture Channel 3 FIFO Top */
#define Val_CAP1FBOT (volatile unsigned int *) 0x7427 /* Bottom reg. pf capture FIFO stack 1 */
#define Val_CAP2FBOT (volatile unsigned int *) 0x7427 /* Bottom reg. pf capture FIFO stack 2 */
#define Val_CAP3FBOT (volatile unsigned int *) 0x7427 /* Bottom reg. pf capture FIFO stack 3 */
#define Val_EVAIMRA (volatile unsigned int *) 0x742C /* Group A Interrupt Mask Register A */
#define Val_EVAIMRB (volatile unsigned int *) 0x742D /* Group B Interrupt Mask Register A */
#define Val_EVAIMRC (volatile unsigned int *) 0x742E /* Group C Interrupt Mask Register A */
#define Val_EVAIFRA (volatile unsigned int *) 0x742F /* Group A Interrupt Flag Register A */
#define Val_EVAIFRB (volatile unsigned int *) 0x7430 /* Group B Interrupt Flag Register A */
#define Val_EVAIFRC (volatile unsigned int *) 0x7431 /* Group C Interrupt Flag Register A */
#define Val_GPTCONB (volatile unsigned int *) 0x7500 /* GP Timer control register B . */
#define Val_T3CNT (volatile unsigned int *) 0x7501 /* GP Timer 3 counter register. */
#define Val_T3CMPR (volatile unsigned int *) 0x7502 /* GP Timer 3 compare register. */
#define Val_T3PR (volatile unsigned int *) 0x7503 /* GP Timer 3 period register. */
#define Val_T3PER (volatile unsigned int *) 0x7503 /* GP Timer 3 period register. */
#define Val_T3CON (volatile unsigned int *) 0x7504 /* GP Timer 3 control register. */
#define Val_T4CNT (volatile unsigned int *) 0x7505 /* GP Timer 4 counter register. */
#define Val_T4CMPR (volatile unsigned int *) 0x7506 /* GP Timer 4 compare register. */
#define Val_T4PR (volatile unsigned int *) 0x7507 /* GP Timer 4 period register. */
#define Val_T4PER (volatile unsigned int *) 0x7507 /* GP Timer 4 period register. */
#define Val_T4CON (volatile unsigned int *) 0x7508 /* GP Timer 4 control register. */
#define Val_COMCONB (volatile unsigned int *) 0x7511 /* Compare control register B. */
#define Val_ACTRB (volatile unsigned int *) 0x7513 /* Full compare action control register*/
#define Val_DBTCONB (volatile unsigned int *) 0x7515 /* Dead-band timer control register B. */
#define Val_CMPR4 (volatile unsigned int *) 0x7517 /* Full compare unit compare register1 */
#define Val_CMPR5 (volatile unsigned int *) 0x7518 /* Full compare unit compare register2 */
#define Val_CMPR6 (volatile unsigned int *) 0x7519 /* Full compare unit compare register3 */
#define Val_CAPCONB (volatile unsigned int *) 0x7520 /* Capture control register B. */
#define Val_CAPFIFOB (volatile unsigned int *) 0x7522 /* Capture FIFO status register B. */
#define Val_CAP4FIFO (volatile unsigned int *) 0x7523 /* Capture Channel 1 FIFO Top B */
#define Val_CAP5FIFO (volatile unsigned int *) 0x7524 /* Capture Channel 2 FIFO Top B */
#define Val_CAP6FIFO (volatile unsigned int *) 0x7525 /* Capture Channel 3 FIFO Top B */
#define Val_CAP4FBOT (volatile unsigned int *) 0x7527 /* Bottom reg. pf capture FIFO stack 1 */
#define Val_CAP5FBOT (volatile unsigned int *) 0x7527 /* Bottom reg. pf capture FIFO stack 2 */
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