dsp240x_sysctrl.h

使用TI DSP 2407A 进行开发的源代码

//###########################################################################
//
// FILE:   DSP281x_SysCtrl.h
//
// TITLE:  DSP281x Device System Control Register Definitions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha)
//      |             |      | Added bit definitions for the PLLCR register,
//      |             |      | Low power mode LPMCR0 and LPMCR1 registers
//      |             |      | Corrected OTPWAIT bit field name in FOTPWAIT
//      |             |      | Changed SCIENCLKA to SCIAENCLK and SCIENCLKB to
//      |             |      |    SCIBENCLK to match documentation
//      |             |      | Removed bit definition for SCSR register.  This
//      |             |      |    register should only be written to using a
//      |             |      |    mask value else a read-modify-write will clear
//      |             |      |    the WDOVERRIDE bit. 
//###########################################################################

#ifndef DSP240x_SYS_CTRL_H
#define DSP240x_SYS_CTRL_H


#ifdef __cplusplus
extern "C" {
#endif


//---------------------------------------------------------------------------
// System Control Individual Register Bit Definitions:
//

struct IMR_BITS  { //interrupt mask reg bit definitions:
	Uint16 INT1MASK :1;   //0
	Uint16 INT2MASK :1;   //0
	Uint16 INT3MASK :1;   //0
	Uint16 INT4MASK :1;   //0
	Uint16 INT5MASK :1;   //0
	Uint16 INT6MASK :1;   //0
	Uint16 rsvd :10;
};


union IMR_REG {
   Uint16              all;
   struct IMR_BITS     bit;
}; 


struct IFR_BITS  { //interrupt mask reg bit definitions:
	Uint16 INT1FLAG :1;   //0
	Uint16 INT2FLAG :1;   //0
	Uint16 INT3FLAG :1;   //0
	Uint16 INT4FLAG :1;   //0
	Uint16 INT5FLAG :1;   //0
	Uint16 INT6FLAG :1;   //0
	Uint16 rsvd :10;
};

union IFR_REG {
   Uint16              all;
   struct IFR_BITS     bit;
}; 


// Peripheral system control register 1 bit definitions:
struct SCSR1_BITS  {   // bits  description
   Uint16 ILLADR :1;      // 0    ill address
   Uint16 rsvd1 :1;      // 1      reserved
   Uint16 EVAENCLK :1;   // 2     Enable high speed clk to EV-A
   Uint16 EVBENCLK :1;   // 3     Enable high speed clk to EV-B
   Uint16 CANENCLK :1;   // 4      Enable system clk to eCAN
   Uint16 SPIENCLK :  1;   // 5     Enable low speed clk to SPI
   Uint16 SCIENCLK :1;   // 6      Enable low speed clk to SCI-A
   Uint16 ADCENCLK :1;   // 7     Enable high speed clk to ADC
   Uint16 rsvd2 :1;      // 8     reserved
   Uint16 CLKPS :3;      // 9-11  PLL Clock select 
   Uint16 LPM :2;        // 12,13     Low Power Mode
   Uint16 CLKSRC:1;      // 14   reserved
   Uint16 rsvd3:1;       // 15     reserved
 
};

union SCSR1_REG {
   Uint16             all;
   struct SCSR1_BITS  bit;
};   

// Peripheral system control register 2 bit definitions:
struct SCSR2_BITS  {   // bits  description
   Uint16 SETSARAM : 2;      // 0-1   data/program select
   Uint16 MP1_MC0 : 1;      // 2     micro controller or micro computer
   Uint16 BOOT_EN : 1;   // 3    boot enable
   Uint16 XMIF_HI : 1;   // 4    xmif high blocked
   Uint16 WD_OVERRIDE : 1;   // 5     watch dog protect
   Uint16 IP_QUAL : 1;   // 6     input clock limit
   Uint16 rsvd : 9;   // 7-15     
 
};

union SCSR2_REG {
   Uint16              all;
   struct SCSR2_BITS  bit;
}; 


// Peripheral system control register 2 bit definitions:
struct WDCR_BITS  {   // bits  description
   Uint16 WDPS :3;      // 0-2   watch dog clock
   Uint16 WDCHK :3;      // 3-5     must write 101,or reset
   Uint16 WDDIS :1;   // 6    =1,disable watchdog,=0,enable watch dog
   Uint16 WDFLAG :1;   // 7    wd reset status 
   Uint16 rsvd :8;   // 8-15     
 
};

union WDCR_REG {
   Uint16              all;
   struct WDCR_BITS  bit;
};     


//---------------------------------------------------------------------------
// System Control Register File:
//
struct SYS_CTRL_REGS {

	Uint16    PIRQR0;  //外设中断请求寄存器0 7010h	
    Uint16    PIRQR1;  //外设中断请求寄存器1 7011h
    Uint16    PIRQR2;	//外设中断请求寄存器2 7012h
    Uint16    rsvd1;                /* 0x7093 in data space */
    Uint16    PIACKR0;  //外设中断应答寄存器0 7014h
    Uint16    PIACKR1;  	//外设中断应答寄存器1 7015h
    Uint16    PIACKR2;	//外设中断应答寄存器2 7016h
    Uint16    rsvd2;       /* 0x7058 in data space */
    union     SCSR1_REG;	//系统控制与状态寄存器1 7018h
	union     SCSR2_REG; //系统控制与状态寄存器2 7019h
	Uint16    rsvd3;	/*;I/O port B Data & Direction reg.*/
	Uint16    rsvd4;               /* 0x7058 in data space */
	Uint16    DINR;	//系统模块状态寄存器 701ch
	Uint16    rsvd5;              /* 0x7058 in data space */
	Uint16    PIVR; //外设中断向量寄存器 701eh	

	Uint16    rsvd6[4];            // 0-9   
	Uint16    WDCNTR;    // 19: WD counter register
    Uint16    rsvd7;     // 20
    Uint16    WDKEY;     // 21: WD reset key register
    Uint16    rsvd8[3];  // 22-24
   // No bit definitions are defined for WDCR because
   // the proper value must be written to the WDCHK field
   // whenever writing to this register. 
    union             WDCR;      // 25: WD timer control register 
};

struct SYS_INT_REGS {
	union  IMR_REG;
	Uint16 rsvd;
	union  IFR_REG;
};

//---------------------------------------------------------------------------
// System Control External References & Function Declarations:
//
//extern volatile struct SYS_CTRL_REGS  * SysCtrlRegs;
//extern volatile struct SYS_INT_REGS   * SysIntRegs;

//extern volatile struct FLASH_REGS FlashRegs;


#ifdef __cplusplus
}
#endif /* extern "C" */

#endif  // end of DSP281x_SYS_CTRL_H definition

//===========================================================================
// No more.
//===========================================================================