x9002.vhd

X9002 VHDL coed fskdflsdkfsldfksdf sdfsd

    IB1 : IBUFG
        port map (
            I           => pclk_in,
            O           => pclk_in_b
        );

    IB2 : IBUF
        port map (
            I           => rst_in,
            O           => rst_in_b
        );
            
    --
    -- The DCM provides a de-skewed word rate clock output and two 5X clock 
    -- outputs shifted 180 degrees from each other to drive the DDR blocks.
    --


    DCM1 : DCM
    -- synthesis translate_off
        generic map (
            DLL_FREQUENCY_MODE  => "LOW",
            STARTUP_WAIT        => false,
            CLKFX_MULTIPLY      => 5,
            CLKFX_DIVIDE        => 1
        )
    -- synthesis translate_on
        port map ( 
            CLKIN       => pclk_in_b,
            CLKFB       => clk,
            RST         => rst_in_b,
            CLK0        => clk0,
            CLK90       => open,
            CLK180      => open,
            CLK270      => open,
            CLK2X       => open,
            CLK2X180    => open,
            CLKDV       => open,
            CLKFX       => clkfx,
            CLKFX180    => clkfx180,
            LOCKED      => locked1,
            PSDONE      => open,
            STATUS      => open
        );


    --
    -- Instantiate the global clock buffers
    --
    BG1 : BUFG
        port map (
            I           => clk0,
            O           => clk
        );

    BG2 : BUFG
        port map (
            I           => clkfx,
            O           => clk5x
        );

    BG3 : BUFG
        port map (
            I           => clkfx180,
            O           => clk5x180
        );


    --
    -- Generate the local reset signal from the rst_in_b and DCM locked signals.
    --
    rst <= rst_in_b or not locked_int;

    --
    -- Input register
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            din <= (others => '0');
        elsif (clk'event and clk = '1') then
            din <= pd;
        end if;
    end process;

    din_msb8 <= din(9 downto 2);

    --
    -- TRS detector and clipper
    --
    all_zeros <= '1' when (din_msb8 = (din_msb8'range => '0')) else
                 '0';

    all_ones  <= '1' when (din_msb8 = (din_msb8'range => '1')) else
                 '0';

    trs_det <= not (all_zeros or all_ones);

    process(all_zeros, all_ones, clip_en, din)
    begin
        if (clip_en = '0' and all_zeros = '1') then
            clip_out <= "00";
        elsif (clip_en = '0' and all_ones = '1') then
            clip_out <= "11";
        else
            clip_out <= din(1 downto 0);
        end if;
    end process;

    clipped <= din_msb8 & clip_out;

    --
    -- Instantiate the half-bit rate serial scrambler
    --
    SCRM : ser_scrambler2
        port map (
            clk         => clk5x,
            rst         => rst,
            ld          => load,
            nrzi        => not_bypass,
            scram       => not_bypass,
            d           => clipped,
            q           => scram_out
        );

    not_bypass <= not bypass;

    --
    -- Generate a load enable signal for the serial scrambler
    --
    process(clk, preload_rst)
    begin
        if (preload_rst = '1') then
            preload <= '0';
        elsif (clk'event and clk = '1') then
            preload <= '1';
        end if;
    end process;

    preload_rst <= rst or load;

    process(clk5x, rst)
    begin
        if (rst = '1') then
            load <= '0';
        elsif (clk5x'event and clk5x = '1') then
            if (clk = '1' and load = '0' and preload = '1') then
                load <= '1';
            else
                load <= '0';
            end if;
        end if;
    end process;

    --
    -- Instantiate the data DDR flip-flops
    --
    DDR1 : FDDRCPE
        port map (
            Q           => sdo,
            C0          => clk5x,
            C1          => clk5x180,
            CE          => VCC,
            CLR         => rst,
            D0          => scram_out(0),
            D1          => scram_out(1),
            PRE         => GND
        );

    --
    -- Instantiate the LVPECL output buffer for the data
    --
    OB1 : OBUFDS
        port map (
            O           => sdo_p,
            OB          => sdo_n,
            I           => sdo
        );

    --
    -- This DCM doubles the clkfx clock to generate a bit-rate clock. Note that 
    -- this clock is simply used to output a bit-rate clock for reference
    -- purposes. The bit-rate clock is not requred to generate the SDI 
    -- bitstream. Driving the DDR flip-flops with both CLK2X and CLK2X180
    -- from this DCM achieves a nearly 50% duty cycle.

    dcm2_rst <= rst_in_b or not locked1;

    DCM2 : DCM
    -- synthesis translate_off
        generic map (
            DLL_FREQUENCY_MODE  => "LOW",
            STARTUP_WAIT        => false
        )
    -- synthesis translate_on
        port map ( 
            CLKIN       => clk5x,
            CLKFB       => clk10x,
            RST         => dcm2_rst,
            CLK0        => open,
            CLK90       => open,
            CLK180      => open,
            CLK270      => open,
            CLK2X       => clk10x_u,
            CLK2X180    => clk10x180_u,
            CLKDV       => open,
            CLKFX       => open,
            CLKFX180    => open,
            LOCKED      => locked2,
            PSDONE      => open,
            STATUS      => open
        );


    --
    -- Instantiate the global clock buffers
    --
    BG4 : BUFG
        port map (
            I           => clk10x_u,
            O           => clk10x
        );

    BG5 : BUFG
        port map (
            I           => clk10x180_u,
            O           => clk10x180
        );

    --
    -- Instantiate the clock DDR flip-flops.
    --
    DDR2 : FDDRCPE
        port map (
            Q           => sck,
            C0          => clk10x,
            C1          => clk10x180,
            CE          => VCC,
            CLR         => rst,
            D0          => VCC,
            D1          => GND,
            PRE         => GND
        );

    --
    -- Instantiate the LVPECL output buffer for the clock
    --
    OB2 : OBUFDS
        port map (
            O           => sck_p,
            OB          => sck_n,
            I           => sck
        );
    
    --
    -- Instantiate a LVPECL output buffer for the sync_det output
    --
    OB3 : OBUF
        port map (
            O           => sync_det,
            I           => trs_det
        );


    locked_int <= locked1 and locked2;
    locked <= locked_int;

end synth;