x9002.vhd

X9002 VHDL coed fskdflsdkfsldfksdf sdfsd

--------------------------------------------------------------------------------
-- X9002.vhd
--
-- SMPTE-259M Scrambler
--
--
--
--                  Author: John F. Snow
--                  Staff Applications Engineer
--
--                  Video Applications
--                  Advanced Products Group
--                  Xilinx, Inc.
--
--                  Copyright (c) 2001 Xilinx, Inc.
--                  All rights reserved
--
--                  Date:   Oct. 11, 2001
--
--                  RESTRICTED RIGHTS LEGEND
--
--      This software has not been published by the author, and 
--      has been disclosed to others for the purpose of enhancing 
--      and promoting design productivity in Xilinx products.
--
--      Therefore use, duplication or disclosure, now and in the 
--      future should give consideration to the productivity 
--      enhancements afforded the user of this code by the author's 
--      efforts.  Thank you for using our products !
--
-- Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
--          Oct. 11, 2001     Creation
--
--
-- Other modules instanced in this design:
--
--          ser_scrambler2
--
--------------------------------------------------------------------------------
--
-- Description of module:
-- 
-- This module is an example of how the SDI parallel scrambler module can be 
-- used as an alternative to a commercially available SDI encoder chip.
-- 
-- The X9002 accepts 8-bit or 10-bit digital video data synchronously with the
-- pclk_in signal and loads it into an input register. The data then passes 
-- through TRS clipper circuit, a parallel to serial converter, and a SDI 
-- scrambler. 
-- 
-- The X9002 module implemented here uses the ser_scrambler2 module which runs
-- at half the bit rate of the SDI link. A DCM multiplies the incoming parallel 
-- clock by five. DDR flip-flops in the IOB are used to generate the full 
-- bit-rate serial bit stream. The X9002 also outputs a differential LVPECL 
-- serial clock output for reference purposes. DDR flip-flops are used in this 
-- module to generate this full bit-rate clock output. This does consume a 
-- second DCM that can be removed from the design if the bit-rate clock output
-- is not needed.
-- 
-- This module has the following inputs and outputs:
-- 
-- pclk_in: input data clock that loads all registers in the module.
-- 
-- pd[9:0]: input data word loaded into the input register on rising edge of
--          pclk_in.
-- 
-- bypass:  when this input is high the SDI scrambler is bypassed and the data
--          loaded into the input register is serialized without being 
--          scrambled. 
-- 
-- clip_en: when this input is low the TRS clipper function is enabled. 
-- 
-- sync_det:this output is asserted low for when the input register contains all
--          zeros or all ones in the MS 8-bits.
-- 
-- sdo_p/sdo_n: differential serial data output pair.
-- 
-- sck_p/sck_n: differential serial clock output pair
-- 
-- 
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

library unisim;
use unisim.all;

entity X9002 is
    port (
        pclk_in:    in  std_ulogic;                     -- clock input
        rst_in:     in  std_ulogic;                     -- reset input
        bypass:     in  std_ulogic;                     -- bypasses SDI encoding when High
        clip_en:    in  std_ulogic;                     -- enables TRS clipping when Low
        pd:         in  std_ulogic_vector(9 downto 0);  -- input data bus
        sync_det:   out std_ulogic;                     -- TRS detected output
        locked:     out std_ulogic;                     -- DCMs are locked when 1
        sdo_p:      out std_ulogic;                     -- serial data output true
        sdo_n:      out std_ulogic;                     -- serial data output complement
        sck_p:      out std_ulogic;                     -- serial clock output true
        sck_n:      out std_ulogic                      -- serial clock output complement   
    );
end X9002;

architecture synth of X9002 is

-- Component declarations
component IBUFG
   port(
      O :           out std_ulogic;
      I :           in  std_ulogic);
end component;

component IBUF
   port(
        O :         out std_ulogic;
        I :         in  std_ulogic
   );
end component;

component BUFG
   port(
        O :         out std_ulogic;
        I :         in  std_ulogic
   );
end component;

component DCM
-- synthesis translate_off
    generic (
        DLL_FREQUENCY_MODE :    string  := "LOW";
        STARTUP_WAIT :          boolean := false;
        CLKFX_MULTIPLY :        integer := 4 ;
        CLKFX_DIVIDE :          integer := 1
    );
-- synthesis translate_on
    port ( 
        CLKIN :     in  std_ulogic := '0';
        CLKFB :     in  std_ulogic := '0';
        DSSEN :     in  std_ulogic := '0';
        PSINCDEC :  in  std_ulogic := '0';
        PSEN :      in  std_ulogic := '0';
        PSCLK :     in  std_ulogic := '0';
        RST :       in  std_ulogic := '0';
        CLK0 :      out std_ulogic;
        CLK90 :     out std_ulogic;
        CLK180 :    out std_ulogic;
        CLK270 :    out std_ulogic;
        CLK2X  :    out std_ulogic;
        CLK2X180 :  out std_ulogic;
        CLKDV :     out std_ulogic;
        CLKFX :     out std_ulogic;
        CLKFX180 :  out std_ulogic;
        LOCKED :    out std_ulogic;
        PSDONE :    out std_ulogic;
        STATUS :    out std_logic_vector(7 downto 0)
    );
end component;

component FDDRCPE
   port(
        Q :         out std_ulogic;
        D0 :        in  std_ulogic;
        D1 :        in  std_ulogic;
        C0 :        in  std_ulogic;
        C1 :        in  std_ulogic;
        CE :        in  std_ulogic;
        PRE :       in  std_ulogic;
        CLR :       in  std_ulogic
    );
end component;
    
component OBUFDS
   port(
        O  :        out std_ulogic;
        OB :        out std_ulogic;
        I :         in  std_ulogic
    );
end component;

component OBUF
    port(
        O :         out std_ulogic;
        I :         in  std_ulogic
);
end component;

component ser_scrambler2
    port (
        clk:        in  std_ulogic;                     -- clock input
        rst:        in  std_ulogic;                     -- async reset input
        ld:         in  std_ulogic;                     -- load enable input
        nrzi:       in  std_ulogic;                     -- enables NRZ-to-NRZI conversion when high
        scram:      in  std_ulogic;                     -- enables scrambler when high
        d:          in  std_ulogic_vector(9 downto 0);  -- input data bus
        q:          out std_ulogic_vector(1 downto 0)   -- output data
    );
end component;

-- DCM attributes

attribute CLKFX_MULTIPLY :      integer;
attribute CLKFX_DIVIDE :        integer;
attribute DLL_FREQUENCY_MODE :  string;
attribute STARTUP_WAIT :        string;

attribute CLKFX_MULTIPLY of DCM1 :      label is 5;
attribute CLKFX_DIVIDE of DCM1 :        label is 1;
attribute DLL_FREQUENCY_MODE of DCM1 :  label is "LOW";
attribute STARTUP_WAIT of DCM1 :        label is "FALSE";

attribute DLL_FREQUENCY_MODE of DCM2 :  label is "LOW";
attribute STARTUP_WAIT of DCM2 :        label is "FALSE";

attribute IOSTANDARD :          string;
attribute IOSTANDARD of OB1 :   label is "LVDS_25"; --"LVPECL_33";
attribute IOSTANDARD of OB2 :   label is "LVDS_25"; --"LVPECL_33";
attribute IOSTANDARD of OB3 :   label is "LVDS_25"; --"LVPECL_33";

-- Internal signals
signal din :            std_ulogic_vector(9 downto 0);  -- data input register
signal din_msb8 :       std_ulogic_vector(7 downto 0);  -- 8 MSBs of din reg
signal pclk_in_b :      std_ulogic;                     -- Input clock after IBUF
signal clk0 :           std_ulogic;                     -- Unbuffered DCM clk0 output
signal clkfx :          std_ulogic;                     -- Unbuffered DCM clkfx output
signal clkfx180 :       std_ulogic;                     -- Unbuffered DCM clkfx180 output
signal clk :            std_ulogic;                     -- Buffered clk0 signal
signal clk5x :          std_ulogic;                     -- Buffered 5X clock
signal clk5x180 :       std_ulogic;                     -- Buffered 5X clock complement
signal clk10x_u :       std_ulogic;                     -- Unbuffered 10X clock
signal clk10x180_u :    std_ulogic;                     -- Unbuffered 10X clock complement
signal clk10x :         std_ulogic;                     -- Buffered 10X clock
signal clk10x180 :      std_ulogic;                     -- Buffered 10X clock complement
signal rst_in_b :       std_ulogic;                     -- Buffered reset signal
signal clip_out :       std_ulogic_vector(1 downto 0);  -- Clipper output
signal clipped :        std_ulogic_vector(9 downto 0);  -- Clipped data into scrambler
signal scram_out :      std_ulogic_vector(1 downto 0);  -- Scrambler output
signal sdo :            std_ulogic;                     -- Data out of DDR mux to LVPECL buffer
signal locked1 :        std_ulogic;                     -- DCM1 is locked
signal locked2 :        std_ulogic;                     -- DCM2 is locked
signal locked_int :     std_ulogic;                     -- internal version of locked
signal rst :            std_ulogic;                     -- Combination of rst_in and DCM locked
signal load :           std_ulogic;                     -- Load enable to serial scrambler
signal preload :        std_ulogic;                     -- Trigger signal used to generate load
signal preload_rst :    std_ulogic;                     -- Reset signal for preload
signal all_ones :       std_ulogic;                     -- 1 when din[9:2] are all 1s
signal all_zeros :      std_ulogic;                     -- 1 when din[9:2] are all 0s
signal trs_det :        std_ulogic;                     -- 0 when all_ones or all_zeros
signal sck :            std_ulogic;                     -- Serial clock
signal dcm2_rst :       std_ulogic;                     -- Reset input to DCM2
signal not_bypass :     std_ulogic;                     -- inverse of bypass input

signal VCC :            std_ulogic;
signal GND :            std_ulogic;

begin

    VCC <= '1';
    GND <= '0';
        
    --
    -- The IBUFG buffers the clk_in signal.
    --