📄 vr4122io.h
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// VRC4122 register definition
// Platform independent
#ifndef _VR4122IO_H_
#define _VR4122IO_H_
// Internal I/O size
#define INTIOSIZE 0x2000
// Internal I/O offset address
#define BCUCNTREG1 0x0000
#define ROMSIZEREG 0x0004
#define ROMSPEEDREG 0x0006
#define IO0SPEEDREG 0x0008
#define IO1SPEEDREG 0x000A
#define REVIDREG 0x0010
#define CLKSPEEDREG 0x0014
#define BCUCNTREG3 0x0016
#define CSIIBALREG 0x0020
#define CSIIBAHREG 0x0022
#define CSIIALREG 0x0024
#define CSIIAHREG 0x0026
#define CSIOBALREG 0x0028
#define CSIOBAHREG 0x002A
#define CSIOALREG 0x002C
#define CSIOAHREG 0x002E
#define FIRBALREG 0x0030
#define FIRBAHREG 0x0032
#define FIRALREG 0x0034
#define FIRAHREG 0x0036
#define RAMBALREG 0x01E0
#define RAMBAHREG 0x01E2
#define RAMALREG 0x01E4
#define RAMAHREG 0x01E6
#define IOBALREG 0x01E8
#define IOBAHREG 0x01EA
#define IOALREG 0x01EC
#define IOAHREG 0x01EE
#define DMARSTREG 0x0040
#define DMAIDLEREG 0x0042
#define DMASENREG 0x0044
#define DMAMSKREG 0x0046
#define DMAREQREG 0x0048
#define DMATDREG 0x004A
#define DMAABITREG 0x004C
#define DMACONTROLREG 0x004E
#define BASSCNTLREG 0x0050
#define BASSCNTHREG 0x0052
#define CURRENTCNTLREG 0x0054
#define CURRENTCNTHREG 0x0056
#define DMATCINTRREG 0x0058
#define CMUCLKMSK 0x0060
#define ICU_SYSINT1REG 0x0080
#define ICU_GIUINTLREG 0x0088
#define ICU_DSIUINTREG 0x008A
#define ICU_MSYSINT1REG 0x008C
#define ICU_MGIUINTLREG 0x0094
#define ICU_MDSIUINTREG 0x0096
#define ICU_NMIREG 0x0098
#define ICU_SOFTINTREG 0x009A
#define ICU_SYSINT2REG 0x00A0
#define ICU_GIUINTHREG 0x00A2
#define ICU_FIRINTREG 0x00A4
#define ICU_MSYSINT2REG 0x00A6
#define ICU_MGIUINTHREG 0x00A8
#define ICU_MFIRINTREG 0x00AA
#define ICU_PCIINTREG 0x00AC
#define ICU_SCUINTREG 0x00AE
#define ICU_CSIINTREG 0x00B0
#define ICU_MPCIINTREG 0x00B2
#define ICU_MSCUINTREG 0x00B4
#define ICU_MCSIINTREG 0x00B6
#define ICU_BCUINTREG 0x00B8
#define ICU_MBCUINTREG 0x00BA
#define PMUINTREG 0x00C0
#define PMUCNTREG 0x00C2
#define PMUINT2REG 0x00C4
#define PMUCNT2REG 0x00C6
#define PMUWAITREG 0x00C8
#define PMUTCLKDIVREG 0x00CC
#define PMUINTRCLKDIVREG 0x00CE
#define ETIMELREG 0x0100
#define ETIMEMREG 0x0102
#define ETIMEHREG 0x0104
#define ECMPLREG 0x0108
#define ECMPMREG 0x010A
#define ECMPHREG 0x010C
#define RTCL1LREG 0x0110
#define RTCL1HREG 0x0112
#define RTCL1CNTLREG 0x0114
#define RTCL1CNTHREG 0x0116
#define RTCL2LREG 0x0118
#define RTCL2HREG 0x011A
#define RTCL2CNTLREG 0x011C
#define RTCL2CNTHREG 0x011E
#define TCLKLREG 0x0120
#define TCLKHREG 0x0122
#define TCLKCNTLREG 0x0124
#define TCLKCNTHREG 0x0126
#define RTCINTREG 0x013E
#define GIUIOSELL 0x0140
#define GIUIOSELH 0x0142
#define GIUPIODL 0x0144
#define GIUPIODH 0x0146
#define GIUINTSTATL 0x0148
#define GIUINTSTATH 0x014A
#define GIUINTENL 0x014C
#define GIUINTENH 0x014E
#define GIUINTTYPL 0x0150
#define GIUINTTYPH 0x0152
#define GIUINTALSELL 0x0154
#define GIUINTALSELH 0x0156
#define GIUINTHTSELL 0x0158
#define GIUINTHTSELH 0x015A
#define GIUPODATEN 0x015C
#define GIUPODATL 0x015E
#define LEDHTSREG 0x0180
#define LEDLTSREG 0x0182
#define LEDCNTREG 0x0188
#define LEDASTCREG 0x018A
#define LEDINTREG 0x018C
#define CSI_MODEREG 0x01A0
#define CSI_CLKSELREG 0x01A1
#define CSI_SIRBREG 0x01A2
#define CSI_SOTBREG 0x01A4
#define CSI_SIRBEREG 0x01A6
#define CSI_SOTBFREG 0x01A8
#define CSI_SIOREG 0x01AA
#define CSI_CNTREG 0x01B0
#define CSI_INTREG 0x01B2
#define CSI_IFIFOVREG 0x01B4
#define CSI_OFIFOVREG 0x01B6
#define CSI_IFIFOREG 0x01B8
#define CSI_OFIFOREG 0x01BA
#define CSI_FIFOTRGREG 0x01BC
#define SDRAMMODEREG 0x0400
#define SDRAMCNTREG 0x0402
#define BCURFCNTREG 0x0404
#define BCURFCOUNTREG 0x0406
#define RAMSIZEREG 0x0408
#define SIURBREG 0x0800
#define SIUTHREG 0x0800
#define SIUDLLREG 0x0800
#define SIUIEREG 0x0801
#define SIUDLMREG 0x0801
#define SIUIIDREG 0x0802
#define SIUFCREG 0x0802
#define SIULCREG 0x0803
#define SIUMCREG 0x0804
#define SIULSREG 0x0805
#define SIUMSREG 0x0806
#define SIUSCREG 0x0807
#define SIUIRSELREG 0x0808
#define SIURESETREG 0x0809
#define SIUCSELREG 0x080A
#define DSIURBREG 0x0820
#define DSIUTHREG 0x0820
#define DSIUDLLREG 0x0820
#define DSIUIEREG 0x0821
#define DSIUDLMREG 0x0821
#define DSIUIIDREG 0x0822
#define DSIUFCREG 0x0822
#define DSIULCREG 0x0823
#define DSIUMCREG 0x0824
#define DSIULSREG 0x0825
#define DSIUMSREG 0x0826
#define DSIUSCREG 0x0827
#define FIRFRSTRREG 0x0840
#define FIRDPINTRREG 0x0842
#define FIRDPCNTRREG 0x0844
#define FIRTDRREG 0x0850
#define FIRRDRREG 0x0852
#define FIRIMRREG 0x0854
#define FIRFSRREG 0x0856
#define FIRIRSR1REG 0x0858
#define FIRCRCSRREG 0x085C
#define FIRFIRCRREG 0x085E
#define FIRMIRCRREG 0x0860
#define FIRDMACRREG 0x0862
#define FIRDMAERREG 0x0864
#define FIRTXIRREG 0x0866
#define FIRRXIRREG 0x0868
#define FIRIFRREG 0x086A
#define FIRRXSTSREG 0x086C
#define FIRTXFLREG 0x086E
#define FIRMRXFREG 0x0870
#define FIRRXFLREG 0x0874
#define PCIMMAW1REG 0x0C00
#define PCIMMAW2REG 0x0C04
#define PCITAW1REG 0x0C08
#define PCITAW2REG 0x0C0C
#define PCIMIOAWREG 0x0C10
#define PCICONFDREG 0x0C14
#define PCICONFAREG 0x0C18
#define PCIMAILREG 0x0C1C
#define BUSERRADREG 0x0C24
#define INTCNTSTAREG 0x0C28
#define PCIEXACCREG 0x0C2C
#define PCIRECONTREG 0x0C30
#define PCIENREG 0x0C34
#define PCICLKSELREG 0x0C38
#define PCITRDYVREG 0x0C3C
#define PCICLKRUNREG 0x0C60
#define PCIUCONFBASE 0x0D00
#define TIMOUTCNTREG 0x1000
#define TIMOUTCOUNTREG 0x1002
#define ERRLADDRESSREG 0x1004
#define ERRHADDRESSREG 0x1006
#define SCUINTREG 0x1008
//
// Internal I/O bit definition
//
#define RFU0 0x0001
#define RFU1 0x0002
#define RFU2 0x0004
#define RFU3 0x0008
#define RFU4 0x0010
#define RFU5 0x0020
#define RFU6 0x0040
#define RFU7 0x0080
#define RFU8 0x0100
#define RFU9 0x0200
#define RFU10 0x0400
#define RFU11 0x0800
#define RFU12 0x1000
#define RFU13 0x2000
#define RFU14 0x4000
#define RFU15 0x8000
// BCUCNTREG1
#define ROMWEN0 0x0010
#define ROMWEN2 0x0040
#define PAGEROM0 0x0100
#define PAGEROM2 0x0400
#define PAGESIZE0 0x1000
#define PAGESIZE1 0x2000
// BCUCNTREG3
#define LCDSEL0 0x0001
#define LCDSEL1 0x0002
#define SYSDIR_EN 0x0008
#define IO32 0x0080
#define EXT_ROMCS0 0x1000
#define EXT_ROMCS1 0x2000
// DMARSTREG
#define DMARST 0x0001
// DMAIDLEREG
#define DMAISTAT 0x0001
// DMASENREG
#define DMASEN 0x0001
// DMAMSKREG
#define DMAMSKFOUT 0x0001
#define DMAMSKCIN 0x0002
#define DMAMSKCOUT 0x0004
#define DMAMSKIOR 0x0008
// DMAREQREG
#define DRQFIR 0x0001
#define DRQCIN 0x0002
#define DRQCOUT 0x0004
#define DRQIOR 0x0008
// DMATDREG
#define TDFIR 0x0001
#define TDIORAM 0x0002
// DMAABITREG
#define DMAPRI_FIXED 0x0000
#define DMAPRI_FIR 0x0001
#define DMAPRI_CIN 0x0002
#define DMAPRI_COUT 0x0004
#define DMAPRI_IOR 0x0008
// CMUMSKREG
#define MSKSIU 0x0002
#define MSKFIR 0x0010
#define MSKDSIU 0x0020
#define MSKCSI 0x0040
#define MSKSSIU 0x0100
#define MSKFFIR 0x0400
#define MSKSDSIU 0x0800
#define MSKSCSI 0x1000
#define MSKPCIU 0x2000
// SYSINT1REG, MSYSINT1REG
#define BATINTR 0x0001
#define POWERINTR 0x0002
#define RTCL1INTR 0x0004
#define ETIMERINTR 0x0008
#define GIUINTR 0x0100
#define SIUINTR 0x0200
#define SOFTINTR 0x0800
#define CLKRUNINTR 0x1000
// SYSINT2REG, MSYSINT2REG
#define RTCL2INTR 0x0001
#define LEDINTR 0x0002
#define TCLKINTR 0x0008
#define FIRINTR 0x0010
#define DSIUINTR 0x0020
#define PCIINTR 0x0040
#define SCUINTR 0x0080
#define CSIINTR 0x0100
#define BCUINTR 0x0200
// NMIREG
#define NMIORINT 0x0001
// SOFTINTREG
#define SOFTINTR0 0x0001
#define SOFTINTR1 0x0002
#define SOFTINTR2 0x0004
#define SOFTINTR3 0x0008
// FIRINTREG, MFIRINTREG
#define FDPINT1 0x0001
#define FDPINT2 0x0002
#define FDPINT3 0x0004
#define FDPINT4 0x0008
#define FIRINT 0x0010
// CSIINTREG, MCSIINTREG
#define RCOVERINT 0x0001
#define RCPAGE1INT 0x0002
#define RCPAGE2INT 0x0004
#define TREMPTYINT 0x0008
#define TRENDINTR 0x0010
#define TRPAGE1INT 0x0020
#define TRPAGE2INT 0x0040
// PMUINTREG
#define POWERSWINTR 0x0001
#define BATTINTR 0x0002
#define RSTSW 0x0008
#define RTCRST 0x0010
#define TIMOUTRST 0x0020
#define MEMO0 0x0040
#define MEMO1 0x0080
#define BATTINH 0x0100
#define RTCINTR 0x0200
#define DCDST 0x0400
#define PMU_CLKRUNINTR 0x0800
#define GPIO0INTR 0x1000
#define GPIO1INTR 0x2000
#define GPIO2INTR 0x4000
#define GPIO3INTR 0x8000
// PMUCNTREG
#define HALTIMERRST 0x0004
#define PLLOFFEN 0x0008
#define STANDBY 0x0080
#define GPIO0TRG 0x0100
#define GPIO1TRG 0x0200
#define GPIO2TRG 0x0400
#define GPIO3TRG 0x0800
#define GPIO0MSK 0x1000
#define GPIO1MSK 0x2000
#define GPIO2MSK 0x4000
#define GPIO3MSK 0x8000
// PMUINT2REG
#define GPIO9INTR 0x1000
#define GPIO10INTR 0x2000
#define GPIO11INTR 0x4000
#define GPIO12INTR 0x8000
// PMUCNT2REG
#define CLKSTOP0 0x0001 // ?
#define CLKSTOP1 0x0002 // ?
#define CLKSTOP2 0x0004 // ?
#define SOFTRST 0x0010
#define GPIO9TRG 0x0100
#define GPIO10TRG 0x0200
#define GPIO11TRG 0x0400
#define GPIO12TRG 0x0800
#define GPIO9MSK 0x1000
#define GPIO10MSK 0x2000
#define GPIO11MSK 0x4000
#define GPIO12MSK 0x8000
// RTCINTREG
#define RTCINTR0 0x0001 // Elapsed Time
#define RTCINTR1 0x0002 // RTCLong1
#define RTCINTR2 0x0004 // RTCLong2
#define RTCINTR3 0x0008 // TClock
// TIMOUTCNTREG
#define TIMOUTE 0x0001
// SCUINTRREG
#define RSVERR 0x0001
#define TIMOERR 0x0002
// SDRAMMODEREG
#define SDRAM_BL_2 0x0001
#define SDRAM_WT 0x0008
#define SDRAM_LT_2 0x0020
#define SDRAM_LT_3 0x0030
#define SDRAM_SCLK 0x8000
// INTCNTSTAREG
#define TABORT 0x01
#define MABORT 0x02
#define RTYRCH 0x04
#define PCISERR 0x08
#define MAILBOX 0x10
#define PARERR 0x20
#define TRDYRCH 0x40
#define IBAMABT 0x80
#define PCIINTMSK_SHIFT 8
#define PCIINTCLR_SHIFT 24
// PCIENREG
#define CONFIG_DONE 0x00000004
// PCICLKRUNREG
#define PCICLKRUN 0x0001
#define PCICLKSTOPEN 0x8000
// SIUIRSELREG
#define SIRSEL 0x0001
#define IRUSESEL 0x0002
#define IRMSEL0 0x0004
#define IRMSEL1 0x0008
#define TMICTX 0x0010
#define TMICMODE 0x0020
// SIURESETREG
#define SRESET 0x0001
// SIUCSELREG
#define CSEL0 0x0040
// FIRIRSR1REG
#define MIR_115200 0x0002 // 115.200kbps
#define MIR_57600 0x0003 // 57.6Kbps
#define MIR_8MHZ 0x0000 // 8MHZ
#define MIR_DISABLE 0x0080 // disable IrDA macro
#define MIR_ENABLE 0x0080 // enable IrDA macro
//
// GPIO bit assignment
// GIUPIODL
#define RESERVE0 0x0001 // GPIO[ 0] Reserved
#define VRC4173INTR 0x0002 // GPIO[ 1] Intr from VRC4173
#define RESERVE2 0x0004 // GPIO[ 2] Reserved
#define RESERVE3 0x0008 // GPIO[ 3] Reserved
#define PCISLOTINTR 0x0010 // GPIO[ 4] PCI Slot INTA
#define FPGAINTR 0x0020 // GPIO[ 5] Intr from FPGA
#define RESERVE6 0x0040 // GPIO[ 6] SDRAM sysdir
#define RESERVE7 0x0080 // GPIO[ 7] SDRAM power
#define RESERVE8 0x0100 // GPIO[ 8] Reserved
#define RESERVE9 0x0200 // GPIO[ 9] Reserved
#define IRPWR 0x0400 // GPIO[10] IrDA power control
#define RESERVE11 0x0800 // GPIO[11] Reserved
#define RESERVE12 0x1000 // GPIO[12] Reserved
#define RESERVE13 0x2000 // GPIO[13] Reserved
#define DCDINTR 0x8000 // GPIO[15] Serial DCD interrupt
#endif // _VR4102IO_H_
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