hardware.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*

	CX5530 hardware defines


*/

#ifndef CX5530_HARDWARE_H
#define CX5530_HARDWARE_H


// the scatter-gather table flags

#define SGD_JMP       0x20000000
#define SGD_EOT       0x80000000	//end of table
#define SGD_EOP       0x40000000	//end of page

typedef struct                  //Format of Scatter and Gather table
{
    unsigned long PhysicalAddr ;  //Base address of this entry
    unsigned long CountAndFlag; //Count and flag of this entry
}   SGD_FORMAT, *PSGD_FORMAT ;


// the device supports 5 audio bus masters; we only use BusMaster0
// BusMaster0 supports 2 codecs; the hardware only has one, so we'll hardcode that

#define PRIMARY_CODEC	0	

#define CODEC_TIMEOUT_COUNT	10	// number of retries during read/write


//******** TOC@@@ NSCE_DEVICE_DEFINES ********

//////////////////////////////////////////////////////////////////
// BRM
#define PCI_CADDR         0x0CF8  // PCI Config address. Pg.177 CPU book.
                                  //  Bits 15..11 specify the PCI device.
                                  //  Bits 7..2 specify reg in PCI device.
#define PCI_CDATA         0x0CFC  // PCI Config data reg, Pg.177 CPU book.
                                  //  After PCI_ADDR set, this reg contains
                                  //  the corresponding data (the dev reg).

                                  // Following is the PCI Bridge (Func 0) ID.
#define CYRIX_VENDOR_ID   0x1078   // CYRIX's PCI Vendor ID.
#define AUDIO_DEVICE_ID     0x0103	// PCI device ID
	                                             // PCI Audio (Func 3) ID.
#define KAH_AUDIO_FUNCTION         0x03	// Audio function

#define BUSMASTER_ERROR			0x02	// mask for the error bit of the busmaster status register
#define BUSMASTER_EOP			0x01	// mask for the EOP bit of the busmaster status register


#pragma pack(1)



// The CODEC commands are actually 16-bit words, into which is inserted
// the codec "target" register, (a byte). The 5530 Codec
// controller writes a command word of 32-bits, that includes the codec
// command word.

union CodecCommand	// describes the codec command register on the Geode CS5530 I/O companion
{
	DWORD dwValue;
	struct
	{
		unsigned Command:16;		// command being sent to codec
		unsigned bCommandValid:1;	// set by hardware when a command is loaded; remains set until the command has been sent
		unsigned reserved:5;
		unsigned Codec:2;	// 00: primary codec, 01: secondary codec, 10 and 11: reserved
		unsigned CommandAddress:8;	// address of the command register where the command is being sent
	}   fields;
};

union CodecStatus 	// describes the codec status register on the Geode CS5530 I/O companion
{
	DWORD dwValue;
	struct
	{
		unsigned Status:16;	// Codec status data, r/o
		unsigned bStatusValid:1;	// status in bits 0:15 is valid (0 == No)
		unsigned bStatusNew:1;	// 1: new status
		unsigned reserved:1;
		unsigned AudioMaster4SlotSelect:1;
		unsigned AudioMaster5SlotSelect:1;
		unsigned bEnableSDATA_IN2:1;
		unsigned bSYNC:1;
		unsigned bAllowSerialInt:1;
		unsigned StatusAddress:8; //address of register for which status is returned
	} fields;
};


union BusMasterCommand
{
	BYTE byValue;
	struct
	{
		unsigned char bBusMaster:1;	// 0: disable; set to 1 to start data transfers. Only set to 0 when the 
								// bus master is paused or at EOT!
		unsigned char reserved:2;	// set to 0
		unsigned char bDirection:1;	// 0: read, 1: write
		unsigned char reserved1:4;
	}   fields;
}; 

struct BusMasterRegisters
{
	union BusMasterCommand regBusMasterCommand;	// Audio bus master command register
	// offset 0x21 BYTE register
	BYTE regBusMasterStatus;	// Audio bus master status register
	// offset 0x22: not used
	WORD wFiller;
	// offset 0x24: DWORD size 
	DWORD regBusMasterPRD;	// Audio bus master  PRD address register
							// pointer to the scatter gather table of physical descriptors address
							// when written, this reg points to the first entry in a PRD table
							// once this audio bus master has been enabled (command reg bit 0 = 1)
							// it loads the pointer and updates the reg to the next PRD by adding 0x08
							// When read, it points to the next PRD
};



// this structure describes a few of the register array of the CS5530
// for more info see the National Semiconductor CS5530 manual, table 100
// (page 189)
// not all registers are used - this driver only handles the 
// AC97 compatible part, with only one bus master
// (because the hardware only uses one codec)


// access to the audio registers is managed through a pointer to a struct AudioRegisters structure
// this structure is defined below. Not all registers are used, so the size of the struct is less than
// the 128 bytes reserved for the hardware registers
// the class that handles the hardware (class CCX5530Audio) has a member pointer to an AudioRegisters structure


struct AudioRegisters
{
	// offset 0;
	union
	{
		DWORD dwValue;
		struct
		{
			unsigned PinStatus:20;	// readonly
			unsigned bStatusValid:1;
			unsigned reserved:9;
			unsigned bAllowSMI: 1;		// 0 : disable interrupt
			unsigned bEnableInterface:1;// 0 : disable interface
		} fields;
	}regCodecGPIOStatus;	// codec GPIO status registers
	// offset 0x04;
	union
	{
		DWORD dwValue;
		struct
		{
			unsigned PinData:20;	// Codec GPIO pin data
			unsigned reserved:12;	// set to 0
		} fields;
	} regCodecGPIOControl;	// codec GPIO control registers
	// offset 0x08;
	union CodecStatus regCodecStatus;	// codec status register
	// offset 0x0C
	union CodecCommand regCodecCommand;	// codec command register
	//offset 0x10 This is a WORD register
	WORD regSMIMirror;	// Second level Audio SMI status mirror register; reading this reg clears status bits
	//offset 0x12 This is a WORD register
	WORD regSMI;	// Second level Audio SMI status register
	// offset 0x14
	DWORD regIOTrap;	// I/O Trap and SMI fast write status register
	// offset 0x18	Word register
	WORD regIOTrapEnable;	//I/O Trap and SMI enable register
	// offset 0x1A	Word register
	WORD regIRQEnable;	//Internal IRQ enable register
	// offset 0x1C	Word register
	WORD regIRQControl;	//Internal IRQ control register
	// offset 0x1E	Word register
	WORD regIRQMask;	//Internal IRQ mask register
	// offset 0x20 BYTE register
	struct BusMasterRegisters busMasters[2];	// two busmasters: 0 for playback, at offset 0x20,
												// 1 for capture, offset 0x28
/*
	union BusMasterCommand regBusMaster0Command;	// Audio bus master 0 command register
	// offset 0x21 BYTE register
	BYTE regBusMaster0Status;	// Audio bus master 0 status register
	// offset 0x22: not used
	WORD wFiller0;
	// offset 0x24: DWORD size 
	DWORD regBusMaster0PRD;	// Audio bus master 0 PRD address register
							// pointer to the scatter gather table of physical descriptors address
							// when written, this reg points to the first entry in a PRD table
							// once audio bus master 0 has been enabled (command reg bit 0 = 1)
							// it loads the pointer and updates the reg to the next PRD by adding 0x08
							// When read, it points to the next PRD
	// offset 0x28 BYTE register
	union BusMasterCommand regBusMaster1Command;	// Audio bus master 1 command register
	// offset 0x29 BYTE register
	BYTE regBusMaster1Status;	// Audio bus master 1 status register
	// offset 0x2A: not used
	WORD wFiller1;
	DWORD regBusMaster1PRD;	// Audio bus master 1 PRD address register
							// pointer to the scatter gather table of physical descriptors address
							// when written, this reg points to the first entry in a PRD table
							// once audio bus master 1 has been enabled (command reg bit 0 = 1)
							// it loads the pointer and updates the reg to the next PRD by adding 0x08
							// When read, it points to the next PRD
*/
};

#pragma pack()

//---
#define  PCI_AUDIO_HDR       0x80009300  // p.52.
#define  PCI_FUNC3_AUDIO     0x300       // p.52. Function 3 of 5530 PCI dev 

#define  PCI_AUDIO_CMD_REG   0x04
#define  MEM_BASE_ADR        0x10

#define  AU_PCI_SMI_DMA_SRC  0x10        // p.107
#define  AU_PCI_SMI_IO_SRC   0x14        // p.107

#define DMA_TABLE_SIZE		4096		// the size allocated for the PRD table

#define  DMA0_CMD            0x20
#define  DMA0_STATUS         0x21
#define  DMA0_PRD_BASE_ADDR  0x24

#define  CAPTURE_FLAG		 0x08		// busmaster command record or play bit

#define  CODEC_CMD_REG       0x0c    // Byte offset in mem mapped audio regs.
#define  CODEC_STATUS        0x08 

#define  CMD_REG_IDX            3
#define  CODEC_STATUS_IDX       2

#define  CMD_MASK            0xFF00FFFF   // low 16-bits are cmd val space, top
                                          //  8 are codec reg to set. Low nibble
                                          //  high-word is codec selector (1of3).

#define  CODEC_RD				0x80		// 1 in the command MSB means "read"

#define MAX_PLAYBACK_CHANNELS		1	// only supports one hardware channel
#define MAX_CAPTURE_CHANNELS		1	// only supports one hardware channel

#define PRIMARY_BUFFER_SIZE 8192


#endif	// CX5530_HARDWARE_H