platinit.c

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-1998  Microsoft Corporation

Module Name:

Abstract:

Functions:


Notes:
    Restrictions/Limitations:
    * Must use National native video driver (not FLAT driver - no VESA BIOS)
    * No audio (requires National VSA code)
    * Assumes single 32MB DIMM (will ignore DIMM in second slot)
   

--*/

#include <windows.h>
#include <pci.h>
#include <pciinit.h>

//
#define FRAMEBUFF_BASE	0x40010000	// Based on GX_BASE of 0x4000.0000

//
// Function prototypes.
//
BOOL InitCS5530(VOID);
BOOL InitPCMCIA(VOID);
int  __cdecl _outp (unsigned short, int);

//
// Globals.
//
ULONG g_nPCI_BUS0_MEM_BASE   = 0xD1000000;
ULONG g_nPCI_BUS0_MEM_LIMIT  = 0xD100FFFF;
ULONG g_nPCI_BUS0_IO_BASE    = 0x0000E000;
ULONG g_nPCI_BUS0_IO_LIMIT   = 0x0000F000;


// Initialize platform
BOOL
PlatformInit(VOID)
{
    ULONG nVal=0;

    //
    // Enumerate and initialize PCI configuration space and allocate resources.
    //
    PciInit();

    //
    // Update MediaGX PCI bridge configuration space
    //
    nVal = PCIConfig_Read(0, 0, 0, 0x40);
    nVal &= 0x00FF0000;		// Keep reserved value.
    nVal |= 0x47001001;		// x-bus burst, x-bus/PCI write buffer, mst
                      		// retry=64 PCI clks, hold x-bus.
    PCIConfig_Write(0, 0, 0, 0x40, nVal);

    //
    // Initialiaze CS5530 (SouthBridge)
    //
    InitCS5530();

    //
    // Initialize Ricoh PCMCIA controller
    //
    InitPCMCIA();

    //
    // Display summary of PCI configuration space for devices found.
    //
    PCIInitListDevicesSummary();

    return(TRUE);
}


// Initialize National CS5530 southbridge
BOOL
InitCS5530(VOID)
{
    ULONG nVal=0;
    PUCHAR pVal=NULL;


    // TODO - clean this up.  The following assumes H26 is strapped low 
    // (IDSEL=AD28) and therefore we use 9 0xxxb instead of 8 0xxxb for our 
    // device numbers.


    //
    // CS5530 F0 (General) configuration space customizations.
    //

    // PCI function control registers and USB shadow.
    PCIConfig_Write(0, 18, 0, 0x40, 0x450C1081);	// PCI intack enable,
							// Allow 16b X/PCI bfr
							// No X-bus arb
							// USB Core on, SA

    // PIT, ISA, ROM, and alternate CPU support.
    PCIConfig_Write(0, 18, 0, 0x50, 0x0BE8447B);	// Gate0 high, ISA div 4
							// Cntr1 port 061H
							// Cntr0 IRQ0
							// 4 PCI clk recov 8b
							// 4 PCI clk revov 16b
							// Fast kbd snoop
							// Enable port 092H
							
    // PCI decode control register.
    nVal = PCIConfig_Read(0, 18, 0, 0x58);
    nVal &= 0x0000FFFF;                                 // Save reserved area.
    nVal |= 0x08030000;					// Pos dec kbd/rtc, IDE
//nVal |= 0x00030000;			        // No IDE
    PCIConfig_Write(0, 18, 0, 0x58, nVal);

    // PCI interrupt steerings.
    nVal = PCIConfig_Read(0, 18, 0, 0x5C);
    nVal &= 0xFFFF0000;		// Save reserved area.
    nVal |= 0x0000AB5F;					// INTA=IRQ15
							// INTB=IRQ5
							// INTC=IRQ11
							// INTD=IRQ10
    PCIConfig_Write(0, 18, 0, 0x5C, nVal);

    // Level sensitive interrupts for PIRQ routing through the PIC.
    _outp(0x4D1, 0x8C);
    _outp(0x4D0, 0x20);

    //
    // CS5530 F1 (ACPI/SMI) configuration space customizations.
    //

    //
    // CS5530 F1BAR (ACPI/SMI mapped regs) configuration space customizations.
    //

    //
    // CS5530 F2 (IDE) configuration space customizations.
    //

    //
    // CS5530 F2BAR (IDE mapped regs) configuration space customizations.
    //

    //
    // CS5530 F3 (Audio) configuration space customizations.
    //

    //
    // CS5530 F3BAR (Audio mapped regs) configuration space customizations.
    //
    //pVal = (PUCHAR)PCIConfig_Read(0, 18, 3, 0x10);
    //*(PULONG)(pVal + 0x08)  = 0x74031901;
    //*(PULONG)(pVal + 0x0C)  = 0x9C000000;
    //*(PUSHORT)(pVal + 0x18) = 0x09DC;
    //*(PUSHORT)(pVal + 0x1A) = 0x0020;
    //*(PULONG)(pVal + 0x24)  = 0x40411700;
    //*(PUCHAR)(pVal + 0x28)  = 0x8;
    //*(PULONG)(pVal + 0x2C)  = 0x40411720;

    //
    // CS5530 F4 (Video) configuration space customizations.
    //
    // CS5530 spec doesn't talk about the fact that this register **MUST** 
    // be mapped to the Frame Buffer address.
    PCIConfig_Write(0, 18, 4, 0x10, FRAMEBUFF_BASE);

    //
    // CS5530 F4BAR (Video mapped regs) configuration space customizations.
    //
    //pVal = (PUCHAR)PCIConfig_Read(0, 18, 4, 0x10);
    //*(PULONG)(pVal + 0x00) = 0x0;
    //*(PULONG)(pVal + 0x04) = 0x8029032F;
    //*(PULONG)(pVal + 0x08) = 0xc800d8;
    //*(PULONG)(pVal + 0x0C) = 0xa510a5;
    //*(PULONG)(pVal + 0x10) = 0x500000;
    //*(PULONG)(pVal + 0x14) = 0x400;
    //*(PULONG)(pVal + 0x18) = 0x0;
    //*(PULONG)(pVal + 0x24) = 0x33915801;
    //*(PULONG)(pVal + 0x28) = 0x100;

    //
    // USB controller configuration space customizations.
    //
    // Set interrupt line number.
    nVal = PCIConfig_Read(0, 19, 0, 0x3c);
    nVal &= 0xFFFFFF00;			// Save reserved values.
    nVal |= 0x0000000F;			// USB ILR=0xF.
    PCIConfig_Write(0, 19, 0, 0x3c, nVal);


    return(TRUE);
}


// Initialize PCMCIA controller (Ricoh R5C476)
BOOL
InitPCMCIA(VOID)
{
    ULONG nVal=0;
   
    // CardBus Bridge 0 
    nVal = PCIConfig_Read(0, 17, 0, 0x3c);
    nVal &= 0xFFFFFF00;
    nVal |= 0x0000000F;
    PCIConfig_Write(0, 17, 0, 0x3c, nVal);
    PCIConfig_Write(0, 17, 0, 0x44, 0x000003E1); 
    PCIConfig_Write(0, 17, 0, 0x80, 0x00240000); 
    PCIConfig_Write(0, 17, 0, 0x88, 0x04630463); 
    PCIConfig_Write(0, 17, 0, 0x90, 0x00722200); 


    // CardBus Bridge 1 
    nVal = PCIConfig_Read(0, 17, 1, 0x3c);
    nVal &= 0xFFFFFF00;
    nVal |= 0x0000000B;
    PCIConfig_Write(0, 17, 1, 0x3c, nVal);
    PCIConfig_Write(0, 17, 1, 0x44, 0x000003E1); 
    PCIConfig_Write(0, 17, 1, 0x80, 0x00240000); 
    PCIConfig_Write(0, 17, 1, 0x88, 0x04630463); 
    PCIConfig_Write(0, 17, 1, 0x90, 0x00722200); 

    return(TRUE);
}