gx.inc

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· INC 代码 · 共 256 行

;
;THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
;ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
;THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
;PARTICULAR PURPOSE.
;Copyright (c) 1995-2000  Microsoft Corporation
;
;Module Name: gx.inc
;
;Abstract: MediaGX assembly support code.
;
;Functions: None.
;
;Notes:
;

; Function Controller Register Base Addresses
GX_BASE                 EQU  040000000H
GX_BASE_ROL             EQU  2

; ScratchPad size
SCPD_BASE		EQU  0400H	; 3KB scratchpad (base = 4KB - 3KB)
SCPD_SIZE_0KB		EQU  00H
SCPD_SIZE_2KB		EQU  01H
SCPD_SIZE_3KB		EQU  02H	; ***
SCPD_SIZE_4KB		EQU  03H

; GX_BASE-based register offsets
PCI_ACCESS_BASE         EQU  (GX_BASE + 01000H)

; Bus Controller
BC_REG_BASE		EQU  (GX_BASE + 08000H)
  BC_DRAM_TOP		EQU  (BC_REG_BASE + 00H)
  BC_XMAP_1		EQU  (BC_REG_BASE + 04H)
  BC_XMAP_2		EQU  (BC_REG_BASE + 08H)
  BC_XMAP_3		EQU  (BC_REG_BASE + 0CH)

; Graphics Pipeline Controller
GP_REG_BASE		EQU  (GX_BASE + 08100H)
  GP_DST		EQU  (GP_REG_BASE + 00H)
  GP_WIDTH		EQU  (GP_REG_BASE + 04H)
  GP_SRC_X		EQU  (GP_REG_BASE + 08H)
  GP_SRC_COLOR_0	EQU  (GP_REG_BASE + 0CH)
  GP_PAT_COLOR_0	EQU  (GP_REG_BASE + 10H)
  GP_PAT_COLOR_2	EQU  (GP_REG_BASE + 14H)
  GP_PAT_DATA_0		EQU  (GP_REG_BASE + 20H)
  GP_PAT_DATA_1		EQU  (GP_REG_BASE + 24H)
  GP_PAT_DATA_2		EQU  (GP_REG_BASE + 28H)
  GP_PAT_DATA_3		EQU  (GP_REG_BASE + 2CH)
  GP_VGA_WRITE		EQU  (GP_REG_BASE + 40H)
  GP_VGA_READ		EQU  (GP_REG_BASE + 44H)
  GP_RASTER_MODE	EQU  (GP_REG_BASE + 100H)
  GP_VECTOR_MODE	EQU  (GP_REG_BASE + 104H)
  GP_BLT_MODE		EQU  (GP_REG_BASE + 108H)
  GP_BLT_STATUS		EQU  (GP_REG_BASE + 10CH)
  GP_VGA_BASE		EQU  (GP_REG_BASE + 110H)
  GP_VGA_LATCH		EQU  (GP_REG_BASE + 114H)

; Display Controller
DC_REG_BASE		EQU  (GX_BASE + 08300H)
  DC_UNLOCK		EQU  (DC_REG_BASE + 00H)
  DC_GENERAL_CFG	EQU  (DC_REG_BASE + 04H)
  DC_TIMING_CFG		EQU  (DC_REG_BASE + 08H)
  DC_OUTPUT_CFG		EQU  (DC_REG_BASE + 0CH)
  DC_FB_ST_OFFSET	EQU  (DC_REG_BASE + 10H)
  DC_CB_ST_OFFSET	EQU  (DC_REG_BASE + 14H)
  DC_CURS_ST_OFFSET	EQU  (DC_REG_BASE + 18H)
  DC_VID_ST_OFFSET	EQU  (DC_REG_BASE + 20H)
  DC_LINE_DELTA		EQU  (DC_REG_BASE + 24H)
  DC_BUF_SIZE		EQU  (DC_REG_BASE + 28H)
  DC_H_TIMING_1		EQU  (DC_REG_BASE + 30H)
  DC_H_TIMING_2		EQU  (DC_REG_BASE + 34H)
  DC_H_TIMING_3		EQU  (DC_REG_BASE + 38H)
  DC_FP_H_TIMING	EQU  (DC_REG_BASE + 3CH)
  DC_V_TIMING_1		EQU  (DC_REG_BASE + 40H)
  DC_V_TIMING_2		EQU  (DC_REG_BASE + 44H)
  DC_V_TIMING_3		EQU  (DC_REG_BASE + 48H)
  DC_FP_V_TIMING	EQU  (DC_REG_BASE + 4CH)
  DC_CURSOR_X		EQU  (DC_REG_BASE + 50H)
  DC_V_LINE_CNT		EQU  (DC_REG_BASE + 54H)
  DC_CURSOR_Y		EQU  (DC_REG_BASE + 58H)
  DC_SS_LINE_CMP	EQU  (DC_REG_BASE + 5CH)
  DC_CURSOR_COLOR	EQU  (DC_REG_BASE + 60H)
  DC_BORDER_COLOR	EQU  (DC_REG_BASE + 68H)
  DC_PAL_ADDRESS	EQU  (DC_REG_BASE + 70H)
  DC_PAL_DATA		EQU  (DC_REG_BASE + 74H)
  DC_DFIFO_DIAG		EQU  (DC_REG_BASE + 78H)
  DC_CFIFO_DIAG		EQU  (DC_REG_BASE + 7CH)

; Memory Controller
MC_REG_BASE		EQU  (GX_BASE + 08400H)
  MC_MEM_CNTRL1		EQU  (MC_REG_BASE + 00H)
  MC_MEM_CNTRL2		EQU  (MC_REG_BASE + 04H)
  MC_BANK_CFG		EQU  (MC_REG_BASE + 08H)
  MC_SYNC_TIM1		EQU  (MC_REG_BASE + 0CH)
  MC_GBASE_ADD		EQU  (MC_REG_BASE + 14H)
  MC_DR_ADD		EQU  (MC_REG_BASE + 18H)
  MC_DR_ACC		EQU  (MC_REG_BASE + 1CH)

; Power Management Controller
PM_REG_BASE		EQU  (GX_BASE + 08500H)
  PM_STAT_SMI		EQU  (PM_REG_BASE + 00H)
  PM_CNTRL_TEN		EQU  (PM_REG_BASE + 04H)
  PM_CNTRL_CSTP		EQU  (PM_REG_BASE + 08H)
  PM_SER_PACK		EQU  (PM_REG_BASE + 0CH)

; MediaGX Configuration Register Indexes (Port Addresses)
 CREG_INDEX_CCR1    EQU   0C1H
 CREG_INDEX_CCR2    EQU   0C2H
 CREG_INDEX_CCR3    EQU   0C3H
 CREG_INDEX_CCR4    EQU   0E8H
 CREG_INDEX_CCR7    EQU   0EBH
 CREG_INDEX_PCR     EQU   020H
 CREG_INDEX_SMHR0   EQU   0B0H
 CREG_INDEX_SMHR1   EQU   0B1H
 CREG_INDEX_SMHR2   EQU   0B2H
 CREG_INDEX_SMHR3   EQU   0B3H
 CREG_INDEX_GCR     EQU   0B8H
 CREG_INDEX_VGACTL  EQU   0B9H
 CREG_INDEX_VGAM0_0 EQU   0BAH
 CREG_INDEX_VGAM0_1 EQU   0BBH
 CREG_INDEX_VGAM0_2 EQU   0BCH
 CREG_INDEX_VGAM0_3 EQU   0BDH
 CREG_INDEX_SMAR0   EQU   0CDH
 CREG_INDEX_SMAR1   EQU   0CEH
 CREG_INDEX_SMAR2   EQU   0CFH
 CREG_INDEX_DIR0    EQU   0FEH
 CREG_INDEX_DIR1    EQU   0FFH

; MediaGX Configuration Register Control and Data Port Addresses
; To access a configuration register, write the creg index to port 022H
; and read/write from port 023H
CREG_ADDR_PORT     EQU   022H
CREG_DATA_PORT     EQU   023H

; CPU-Access Registers
L1_BB0_BASE    EQU   0FFFFFF0CH     ; BLT buffer 0 base address
L1_BB1_BASE    EQU   0FFFFFF1CH     ; BLT buffer 1 base address
L1_BB0_POINTER EQU   0FFFFFF2CH     ; BLT buffer 0 pointer address
L1_BB1_POINTER EQU   0FFFFFF3CH     ; BLT buffer 1 pointer address
PM_BASE        EQU   0FFFFFF6CH     ; Power management base address
PM_MASK        EQU   0FFFFFF7CH     ; Power management address mask

; Display BLT buffer scratchpad offsets
BB0_BASE_OFFSET	   EQU   0400H		; BLT buffer 0 offset into scratchpad
BB1_BASE_OFFSET	   EQU   0930H		; BLT buffer 0 offset into scratchpad

;------------------------------------
; Support Macros
;------------------------------------
; Read from configuration register
; ** Don't use Stack **
CREG_READ       MACRO           Reg, Dest
    xor     al, al
    mov     al, Reg
    out     CREG_ADDR_PORT, al
    xor     al, al
    in      al, CREG_DATA_PORT
    mov     Dest, al
ENDM

;------------------------------------
; Write to configuration register
; ** Don't use Stack **
CREG_WRITE      MACRO           Reg, Src
    xor     ax, ax
    mov     al, Reg
    out     CREG_ADDR_PORT, al
    mov     al, Src
    out     CREG_DATA_PORT, al
ENDM


;-----------------------------------------------------
; Write ULONG to memory-mapped controller register
; ** Don't use Stack **
MMREG_WRITE_32      MACRO           Addr, Src
    xor     eax, eax
    mov     ebx, eax
    mov     eax, Addr
    mov     ebx, Src
    mov     [eax], ebx
ENDM


;-----------------------------------------------------
; Read ULONG to memory-mapped controller register
; ** Don't use Stack **
MMREG_READ_32      MACRO           Addr, Dest
    xor     eax, eax
    mov     ebx, eax
    mov     eax, Addr
    mov     ebx, [eax]
    mov     Dest, ebx
ENDM

PRINT_CREG_VAL      MACRO           Addr
    xor ebx, ebx
    mov bx, Addr
    WriteHex_EBX
    WriteChar ':'
    CREG_READ  Addr, bl
    WriteHex_EBX
    WriteChar 0dH
    WriteChar 0aH
ENDM

PRINT_MMREG_VAL      MACRO           Addr
    xor ebx, ebx
    mov ebx, Addr
    WriteHex_EBX
    WriteChar ':'
    MMREG_READ_32  Addr, ebx
    WriteHex_EBX
    WriteChar 0dH
    WriteChar 0aH
ENDM

; CPU Core Register Access Macros
;-----------------------------------------------------
; CPU_READ macro
; ** Don't use Stack **
; ** Special opcode - requires that scratchpad bits be non-zero (else illegal)
; ** opcode is generated.
CPU_READ      MACRO	; Read processor core register.
    db 0fH
    db 3dH
ENDM

; CPU_WRITE macro
; ** Don't use Stack **
; ** Special opcode - requires that scratchpad bits be non-zero (else illegal)
; ** opcode is generated.
CPU_WRITE      MACRO	; Write to processor core register.
    db 0fH
    db 3cH
ENDM

; CPU_BB0_RESET macro
; ** Don't use Stack **
; ** Special opcode - requires that scratchpad bits be non-zero (else illegal)
; ** opcode is generated.
CPU_BB0_RESET      MACRO	; Reset BLT Buffer 0 pointer to base.
    db 0fH
    db 3aH
ENDM

; CPU_BB1_RESET macro
; ** Don't use Stack **
; ** Special opcode - requires that scratchpad bits be non-zero (else illegal)
; ** opcode is generated.
CPU_BB1_RESET      MACRO	; Reset BLT Buffer 1 pointer to base.
    db 0fH
    db 3bH
ENDM