gxinit.asm

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· 汇编 代码 · 共 381 行

;
;THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
;ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
;THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
;PARTICULAR PURPOSE.
;Copyright (c) 1995-2000  Microsoft Corporation
;
;Module Name: gxinit.asm
;
;Abstract: MediaGX CPU/system setup code.
;
;Functions:
;
;    BridgeConfig
;    BridgePrintConfig
;    InitVideo
;
;Notes:
;

.486p
.model FLAT

INCLUDE         macro.inc
INCLUDE         gx.inc

.code

align 4


BridgeConfig PROC NEAR C PUBLIC

    ;
    ; Program CPU registers
    ; ----------------------------------------------------

    ; CCR3[0] should be 0 to write to some of the following regs
    CREG_WRITE  CREG_INDEX_CCR3,    00H

    CREG_WRITE  CREG_INDEX_CCR1,    02H ; 2
    CREG_WRITE  CREG_INDEX_CCR2,    56H ; 56
    CREG_WRITE  CREG_INDEX_SMAR0,   40H ; 40
    CREG_WRITE  CREG_INDEX_SMAR1,   40H ; 40
    CREG_WRITE  CREG_INDEX_SMAR2,   06H ; 6

    CREG_WRITE  CREG_INDEX_CCR7,    00H ; FF

    CREG_WRITE  CREG_INDEX_VGACTL,  0FFH ; FF
    CREG_WRITE  CREG_INDEX_VGAM0_0, 0FFH ; FF
    CREG_WRITE  CREG_INDEX_VGAM0_1, 0FFH ; FF
    CREG_WRITE  CREG_INDEX_VGAM0_2, 0FFH ; FF
    CREG_WRITE  CREG_INDEX_VGAM0_3, 0FFH ; FF

    ; Program CCR3 with MAPEN on, so we can reach the other regs (off-chip)
    CREG_WRITE  CREG_INDEX_CCR3, 010H

    ; Program configuration registers that rely on MAPEN being on
    CREG_WRITE  CREG_INDEX_CCR4,  0D8H ; D8
    CREG_WRITE  CREG_INDEX_PCR,   00H ; 0
    CREG_WRITE  CREG_INDEX_SMHR0, 00H ; 0
    CREG_WRITE  CREG_INDEX_SMHR1, 00H ; 0 
    CREG_WRITE  CREG_INDEX_SMHR2, 41H ; 41
    CREG_WRITE  CREG_INDEX_SMHR3, 40H ; 40

    ; Initialize 3KB scratchpad (set GCR, preload L1, set up blit buffers)
    mov ebx, GX_BASE
    or  ebx, SCPD_SIZE_3KB
    rol ebx, GX_BASE_ROL
    CREG_WRITE  CREG_INDEX_GCR, bl	; CREG_WRITE uses eax

    ;
    ; Preload L1 cache with scratchpad addresses (blit buffer performance)
    ;
   
    mov eax, GX_BASE 
    mov TR4, eax	; Load GX_BASE as tag
    mov eax, SCPD_BASE
    or al, 1        	; Prep TR5 value

fillCache:
    mov TR5, eax	; Set cache line tag
    add eax, 10h	; Go to next cache line
    cmp eax, 1001h
    jb fillCache	; If at top of cache then we are done


    ; 
    ; Set up both blit buffers (base and pointer)
    ; ---------------------------------------------------
    ; This sets up the L1 cache access to the scratchpad region which
    ; is used, amongst other things, for bitblts, etc.  Setting up the base and
    ; current pointer values requires the GCR to be set up with a non-zero
    ; scratchpad area.  As well, special CPU instructions are required to set
    ; the values.  See Pg. 99.
    ;
    ; Program L1_BB0_BASE
    ;
    mov ebx, L1_BB0_BASE
    mov eax, BB0_BASE_OFFSET
    CPU_WRITE
    ;
    ; Program L1_BB1_BASE
    ;
    mov ebx, L1_BB1_BASE
    mov eax, BB1_BASE_OFFSET
    CPU_WRITE
    ;
    ; Reset L1_BB0_POINTER to base
    ;
    CPU_BB0_RESET
    ;
    ; Reset L1_BB1_POINTER to base
    ;
    CPU_BB1_RESET
    ;
    ; Program PM_BASE
    ;
    mov ebx, PM_BASE
    mov eax, 0
    CPU_WRITE
    ;
    ; Program PM_MASK
    ;
    mov ebx, PM_MASK
    mov eax, 0
    CPU_WRITE

    ; 
    ; Display blit buffer base/pointer addresses
    ;
IF 0
    WriteChar('B')
    WriteChar('l')
    WriteChar('i')
    WriteChar('t')
    WriteChar(' ')
    WriteChar('B')
    WriteChar('u')
    WriteChar('f')
    WriteChar('f')
    WriteChar('e')
    WriteChar('r')
    WriteChar('s')
    WriteChar(':')
    WriteChar(0dH)
    WriteChar(0aH)
    mov ebx, L1_BB0_BASE        ; L1_BB0_BASE
    CPU_READ
    mov ebx, eax
    WriteHex_EBX
    WriteChar(0dH)
    WriteChar(0aH)
    mov ebx, L1_BB1_BASE        ; L1_BB1_BASE
    CPU_READ
    mov ebx, eax
    WriteHex_EBX
    WriteChar(0dH)
    WriteChar(0aH)
    mov ebx, L1_BB0_POINTER     ; L1_BB0_POINTER
    CPU_READ
    mov ebx, eax
    WriteHex_EBX
    WriteChar(0dH)
    WriteChar(0aH)
    mov ebx, L1_BB1_POINTER     ; L1_BB1_POINTER
    CPU_READ
    mov ebx, eax
    WriteHex_EBX
    WriteChar(0dH)
    WriteChar(0aH)
ENDIF

    ; Program CCR3 with MAPEN off
    CREG_WRITE  CREG_INDEX_CCR3, 0E4H


    ;
    ; Program Bridge/Controller Registers (GX_BASE=0x4000.0000)
    ; ---------------------------------------------------------

    ; IBus Controller Registers:

    MMREG_WRITE_32  BC_DRAM_TOP, 07D7FFFFH    ; Gran=128KB TopOfRam=3EB
    MMREG_WRITE_32  BC_XMAP_1,   0000C073H    ; R/W A.0000->A.FFFF , A20M dsbl
    MMREG_WRITE_32  BC_XMAP_2,   00000011H    ; R/O C.0000->C.7FFF (UMB Exp ROM)
    MMREG_WRITE_32  BC_XMAP_3,   33331111H    ; R/O E.0000->E.FFFF,R/WF.0000->F.FFFF
; TODO - dynamically size DRAM.
; *** 128 MB RAM ***
    ;MMREG_WRITE_32  BC_DRAM_TOP, 07D7FFFFH    ; Gran=128KB TopOfRam=3EB
; *** 32 MB RAM ***
    MMREG_WRITE_32  BC_DRAM_TOP, 01D7FFFFH    ; Gran=128KB TopOfRam=EB


    ; Memory Controller Registers:
    MMREG_WRITE_32  MC_MEM_CNTRL1, 00000000H  ; Turn off SDRAM refreshes

    MMREG_WRITE_32  MC_MEM_CNTRL2, 00000021H  ; Sdclkmsks=0
; *** 128 MB RAM ***
    ;MMREG_WRITE_32  MC_BANK_CFG,   00701530H  ; DIM0, 128MB, 8KB page, 1 mod, 4 bank
    ;MMREG_WRITE_32  MC_GBASE_ADD,  000000FBH  ; GBADDR=7D8.0000 > BC_DRAM_TOP
    ;MMREG_WRITE_32  MC_DR_ACC,     000003FEH
; *** 32 MB RAM ***
    MMREG_WRITE_32  MC_BANK_CFG,   00701310H  ; DIM0, 32MB, 2KB page, 1 mod, 4 bank
    MMREG_WRITE_32  MC_GBASE_ADD,  0000003BH  ; GBADDR=1D8.0000 > BC_DRAM_TOP
    MMREG_WRITE_32  MC_DR_ACC,     000003FCH

    MMREG_WRITE_32  MC_SYNC_TIM1,  37533110H  ; Numclks between cycles
    MMREG_WRITE_32  MC_DR_ADD,     000003FFH  ; Index to dirty RAM=3FF

    ; Enable memory refresh, etc.
    MMREG_WRITE_32  MC_MEM_CNTRL1, 0B694390CH ; Set values
    MMREG_WRITE_32  MC_MEM_CNTRL1, 0B696390DH ; Turn on sdclk and program SDRAM
    MMREG_WRITE_32  MC_MEM_CNTRL1, 0B696390CH ; Sdclk on and program done

    ; Initialize video and display splash screen.
    ;EXTRN   _InitVideo:NEAR
    ;NoMemCall _InitVideo

    ; Power Management Registers:
    MMREG_WRITE_32  PM_STAT_SMI,        40008001H
    MMREG_WRITE_32  PM_CNTRL_TEN,       40008019H
    MMREG_WRITE_32  PM_CNTRL_CSTP,      40008000H
    MMREG_WRITE_32  PM_SER_PACK,        40008000H

    NoMemRet

BridgeConfig ENDP


BridgePrintConfig PROC NEAR C PUBLIC

    WriteChar 'B'
    WriteChar 'r'
    WriteChar 'i'
    WriteChar 'd'
    WriteChar 'g'
    WriteChar 'e'
    WriteChar ' '
    WriteChar 'C'
    WriteChar 'o'
    WriteChar 'n'
    WriteChar 'f'
    WriteChar 'i'
    WriteChar 'g'
    WriteChar 'u'
    WriteChar 'r'
    WriteChar 'a'
    WriteChar 't'
    WriteChar 'i'
    WriteChar 'o'
    WriteChar 'n'
    WriteChar ':'
    WriteChar 0dH
    WriteChar 0aH

    ; CPU control registers

    PRINT_CREG_VAL   CREG_INDEX_CCR1
    PRINT_CREG_VAL   CREG_INDEX_CCR2
    PRINT_CREG_VAL   CREG_INDEX_SMAR0
    PRINT_CREG_VAL   CREG_INDEX_SMAR1
    PRINT_CREG_VAL   CREG_INDEX_SMAR2
    PRINT_CREG_VAL   CREG_INDEX_CCR7
    PRINT_CREG_VAL   CREG_INDEX_VGACTL
    PRINT_CREG_VAL   CREG_INDEX_VGAM0_0
    PRINT_CREG_VAL   CREG_INDEX_VGAM0_1
    PRINT_CREG_VAL   CREG_INDEX_VGAM0_2
    PRINT_CREG_VAL   CREG_INDEX_VGAM0_3
    PRINT_CREG_VAL   CREG_INDEX_DIR0
    PRINT_CREG_VAL   CREG_INDEX_DIR1

    ; ** The next set of regs require the MAPEN bit to be unset
    ; Program CCR3 with MAPEN on, so we can reach the other regs (off-chip)
    CREG_WRITE  CREG_INDEX_CCR3, 0F4H

    ; Program configuration registers that rely on MAPEN being on
    PRINT_CREG_VAL   CREG_INDEX_CCR4
    PRINT_CREG_VAL   CREG_INDEX_PCR
    PRINT_CREG_VAL   CREG_INDEX_SMHR0
    PRINT_CREG_VAL   CREG_INDEX_SMHR1
    PRINT_CREG_VAL   CREG_INDEX_SMHR2
    PRINT_CREG_VAL   CREG_INDEX_SMHR3
    PRINT_CREG_VAL   CREG_INDEX_GCR

    ; Program CCR3 with MAPEN off
    ; *** Turn the MAPEN bit back off
    CREG_WRITE  CREG_INDEX_CCR3, 0E4H

    ; Controller Registers

    WriteChar 0dH
    WriteChar 0aH

    ; IBus Controller Registers:
    PRINT_MMREG_VAL   BC_DRAM_TOP
    PRINT_MMREG_VAL   BC_XMAP_1
    PRINT_MMREG_VAL   BC_XMAP_2
    PRINT_MMREG_VAL   BC_XMAP_3

    ; Memory Controller Registers:
    PRINT_MMREG_VAL   MC_MEM_CNTRL1
    PRINT_MMREG_VAL   MC_MEM_CNTRL2
    PRINT_MMREG_VAL   MC_BANK_CFG
    PRINT_MMREG_VAL   MC_SYNC_TIM1
    PRINT_MMREG_VAL   MC_GBASE_ADD
    PRINT_MMREG_VAL   MC_DR_ADD
    PRINT_MMREG_VAL   MC_DR_ACC

    ; Power Management Registers:
    PRINT_MMREG_VAL   PM_STAT_SMI
    PRINT_MMREG_VAL   PM_CNTRL_TEN
    PRINT_MMREG_VAL   PM_CNTRL_CSTP
    PRINT_MMREG_VAL   PM_SER_PACK

    NoMemRet

BridgePrintConfig ENDP


InitVideo PROC NEAR C PUBLIC

    ; Graphics Pipeline Registers:
    MMREG_WRITE_32  GP_DST,            01bd0001H
    MMREG_WRITE_32  GP_WIDTH,          0e0007H
    MMREG_WRITE_32  GP_SRC_X,          01bd0000H
    MMREG_WRITE_32  GP_SRC_COLOR_0,    0ffffH
    MMREG_WRITE_32  GP_PAT_COLOR_0,    0ffffH
    MMREG_WRITE_32  GP_PAT_COLOR_2,    0ffffbfffH
    MMREG_WRITE_32  GP_PAT_DATA_0,     07ff07ffH
    MMREG_WRITE_32  GP_PAT_DATA_1,     07ff07ffH
    MMREG_WRITE_32  GP_PAT_DATA_2,     0ffffffffH
    MMREG_WRITE_32  GP_PAT_DATA_3,     0ffffffffH
    MMREG_WRITE_32  GP_VGA_WRITE,      0f0000ffH
    MMREG_WRITE_32  GP_VGA_READ,       070f0H
    MMREG_WRITE_32  GP_RASTER_MODE,    0550055H
    MMREG_WRITE_32  GP_VECTOR_MODE,    0000000H

    MMREG_WRITE_32  GP_BLT_MODE,       0500050H

    MMREG_WRITE_32  GP_BLT_STATUS,     0000000H
    MMREG_WRITE_32  GP_VGA_BASE,       00H
    MMREG_WRITE_32  GP_VGA_LATCH,      01753H


    ; Display Controller Registers:
    MMREG_WRITE_32  DC_UNLOCK,          04758H ; Unlock DC regs for write.

    MMREG_WRITE_32  DC_GENERAL_CFG,    20006583H
    MMREG_WRITE_32  DC_TIMING_CFG,     02fH
    MMREG_WRITE_32  DC_OUTPUT_CFG,     03005H
    MMREG_WRITE_32  DC_FB_ST_OFFSET,   00H
    MMREG_WRITE_32  DC_CB_ST_OFFSET,   00H
    MMREG_WRITE_32  DC_CURS_ST_OFFSET, 01fff00H
    MMREG_WRITE_32  DC_VID_ST_OFFSET,  010410H
    MMREG_WRITE_32  DC_LINE_DELTA,     0100H
    MMREG_WRITE_32  DC_BUF_SIZE,       052H
    MMREG_WRITE_32  DC_H_TIMING_1,     0347027fH
    MMREG_WRITE_32  DC_H_TIMING_2,     0347027fH
    MMREG_WRITE_32  DC_H_TIMING_3,     02cf028fH
    MMREG_WRITE_32  DC_FP_H_TIMING,    02cf028fH
    MMREG_WRITE_32  DC_V_TIMING_1,     01f301dfH
    MMREG_WRITE_32  DC_V_TIMING_2,     01f301dfH
    MMREG_WRITE_32  DC_V_TIMING_3,     01e301e0H
    MMREG_WRITE_32  DC_FP_V_TIMING,    01e301e0H
    MMREG_WRITE_32  DC_CURSOR_X,       020000140H
    MMREG_WRITE_32  DC_CURSOR_Y,       0200000f0H
    MMREG_WRITE_32  DC_SS_LINE_CMP,    02000eef2H
    MMREG_WRITE_32  DC_CURSOR_COLOR,   01e30000H
    MMREG_WRITE_32  DC_BORDER_COLOR,   01e30000H

    ; Test registers
    MMREG_WRITE_32  DC_PAL_ADDRESS,    025c0105H
    MMREG_WRITE_32  DC_PAL_DATA,       025c7ce5H
    MMREG_WRITE_32  DC_DFIFO_DIAG,     00H
    MMREG_WRITE_32  DC_CFIFO_DIAG,     0ffffffffH

InitVideo ENDP

END