smc8xx.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 216 行

//---------------------------------------------------------------------------
//
//   Copyright 1997, 1998, 1999 Motorola. All Rights Reserved.
//
//   File Name:  smc8xx.h
//
//   Purpose:
//     SMC defines for the MPC8XX processor
//
//---------------------------------------------------------------------------


#ifndef _SMC8XX_H
#define _SMC8XX_H

/*
 * MPC8xx CPM Buffer Descriptor Format
 *
 * - Since BDs are in internal dual-port RAM addresses are munged in
 *    LES mode so the structure elements must be pre-munged as well.
 */

typedef struct SmcBufferDescriptor
{
    volatile unsigned short bd_length;    /* transfer length */
    volatile unsigned short bd_status;    /* control status */
    volatile unsigned char* bd_addr;      /* buffer address */
}
SMC_BD;



/*
 * Defines for SMC1 and SMC2 Port pin assignments
 */

#define SMC1_PORT_B_PINS   (0x00c0)  //MPC821, MPC860, MPC823, MPC850
#define SMC2_PORT_B_PINS   (0x0c00)  //MPC821, MPC860
#define SMC2_PORT_A_PINS   (0x00c0)  //MPC823, MPC850

/*
 * Defines for Baud Rate Generator Clock register
 */

#define SMC_BRGC_COUNT_ENABLE (0x00010000)

/*
 * Defines for Serial Interface Mode Register
 */

#define SIMODE_SMC_MODE_BRG_MASK   (0xf000)
#define SIMODE_SMC1_SHIFT   (0)
#define SIMODE_SMC2_SHIFT   (16)
#define SIMODE_SMCxCS_SHIFT (12)

#define SIMODE_SMC_NMSI_MODE   (0x0000)

#define SIMODE_SMC_BRG1_SELECT   (0x0000)
#define SIMODE_SMC_BRG2_SELECT   (0x1000)
#define SIMODE_SMC_BRG3_SELECT   (0x2000)
#define SIMODE_SMC_BRG4_SELECT   (0x3000)


/*
 * Defines for SMC "UART" Mode Register
 */

#define CLEN_SHIFT  (11)

#define SMC_CHAR_6   ( 6 << CLEN_SHIFT)
#define SMC_CHAR_7   ( 7 << CLEN_SHIFT)
#define SMC_CHAR_8   ( 8 << CLEN_SHIFT)
#define SMC_CHAR_9   ( 9 << CLEN_SHIFT)
#define SMC_CHAR_10  (10 << CLEN_SHIFT)
#define SMC_CHAR_11  (11 << CLEN_SHIFT)
#define SMC_CHAR_12  (12 << CLEN_SHIFT)
#define SMC_CHAR_13  (13 << CLEN_SHIFT)
#define SMC_CHAR_14  (14 << CLEN_SHIFT)
#define SMC_CHAR_15  (15 << CLEN_SHIFT)
#define SMC_CHAR_16  (16 << CLEN_SHIFT)
#define SMC_CHAR_17  (17 << CLEN_SHIFT)

#define SL_SHIFT   (10)

#define SMC_STOP_1   (0 << SL_SHIFT)
#define SMC_STOP_2   (1 << SL_SHIFT)

#define PEN_SHIFT  (8)

#define SMC_PARITY_NONE   (0 << PEN_SHIFT)
#define SMC_PARITY_ODD    (2 << PEN_SHIFT)
#define SMC_PARITY_EVEN   (3 << PEN_SHIFT)

#define SM_SHIFT   (4)

#define SMC_MODE_GCI_SCIT (0 << SM_SHIFT)
#define SMC_MODE_RSVD     (1 << SM_SHIFT)
#define SMC_MODE_UART     (2 << SM_SHIFT)
#define SMC_MODE_TRANS    (3 << SM_SHIFT)

#define DM_SHIFT   (2)

#define DM_NORMAL  (0 << DM_SHIFT)
#define DM_LOOPBK  (1 << DM_SHIFT)
#define DM_ECHO    (2 << DM_SHIFT)

#define SMCMR_TEN   (2)
#define SMCMR_REN   (1)


/********************************************
 * Defines for SMC UART-specific resources
 ********************************************/

/*
 * Defines for SMC UART Receive Buffer Descriptor Control/Status Word
 */

#define RBD_EMPTY   (0x8000)
#define RBD_WRAP    (0x2000)
#define RBD_INT     (0x1000)

#define RBD_CONT    (0x0200)
#define RBD_IDLE    (0x0100)

#define RBD_BREAK   (0x0020)
#define RBD_FRAME   (0x0010)

#define RBD_PARITY  (0x0008)
#define RBD_OVERRUN (0x0002)
#define RBD_CD      (0x0001)

#define RBD_STATUS_ERROR_MASK ( RBD_BREAK | \
                                RBD_FRAME | \
                                RBD_PARITY | \
                                RBD_OVERRUN | \
                                RBD_CD )


/*
 * Defines for SMC UART Transmit Buffer Descriptor Control/Status Word
 */

#define TBD_READY    (0x8000)
#define TBD_WRAP     (0x2000)
#define TBD_INT      (0x1000)

#define TBD_CONT     (0x0200)
#define TBD_PREAMBLE (0x0100)


/*
 * Defines for SMC UART Event/Mask Register
 */

#define EVENT_BRKE  (0x40)
#define EVENT_BRK   (0x10)
#define EVENT_BUSY  (0x04)

#define EVENT_TX    (0x02)
#define EVENT_RX    (0x01)


/*
 * Defines for SMC command opcodes for CPM control register
 */

#define SMC_OPCODE_SHIFT (8)

#define SMC_INIT_RX_TX_PARMS (0 << SMC_OPCODE_SHIFT)
#define SMC_INIT_RX_PARMS    (1 << SMC_OPCODE_SHIFT)
#define SMC_INIT_TX_PARMS    (2 << SMC_OPCODE_SHIFT)
#define SMC_STOP_TX          (4 << SMC_OPCODE_SHIFT)
#define SMC_RESTART_TX       (6 << SMC_OPCODE_SHIFT)
#define SMC_CLOSE_RX_BD      (7 << SMC_OPCODE_SHIFT)

#define SMC_CH_NUM_SHIFT (4)

//
// These are defined in dd_serv.h for OEMIoControl routines
//
// #define SMC1_CH_NUM (9 << SMC_CH_NUM_SHIFT)
// #define SMC2_CH_NUM (13 << SMC_CH_NUM_SHIFT)
//

#define CPCR_FLG_BIT (0x0001)

/*
 * Defines for SMC setup of Byte Order in Rx/Tx function code registers
 */

#define SMC_BO_SHIFT (3)

#define SMC_FC_BO_LE     (0 << SMC_BO_SHIFT)
#define SMC_FC_BO_PPC_LE (1 << SMC_BO_SHIFT)
#define SMC_FC_BO_MOT    (3 << SMC_BO_SHIFT)

/*
 * Defines for access to SMC PRAM array and register array (mpc821.h)
 */

// NOTE:  pram[] and smc_regs[] array bounds are defined in mpc8xx.h, 
//        (i.e., pram[4] and smc_regs[2]), in the pda struct defn.

// pram[4] Array (Page) Index for SMCx -- See 821UM Table B-6 pg. B-14

#define SMC1_PRAM 2
#define SMC2_PRAM 3

// smc_regs[2] Array Index for SMC registers - 821UM Table B-5 pg. B-12

#define SMC1_REGS 0
#define SMC2_REGS 1

#endif      // ifndef _SMC8XX_H