dd_serv.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 490 行

//---------------------------------------------------------------------------
//
//   Copyright 1997, 1999 Motorola. All Rights Reserved.
//
//   File Name:  dd_serv.h
//
//   Purpose:
//     Definitions for MPC8xx and platform abstractions used by drivers.
//
//---------------------------------------------------------------------------



#ifndef _DD_SERV_H
#define _DD_SERV_H

#ifndef ASM_ONLY

//
// Define device identifiers.  Each device (including a device connected
// to an external IRQ interrupt) is defined as one of the following enumerated
// types.  The assigned value was determined by the interrupt indexing scheme
// used by the ISR services of the OAL.
//

typedef enum
{
    CPM_RESERVED   = 0x00,  //ISR dependency: CPM must start as ID 0.
    PARALLEL_PC4   = 0x01,
    PARALLEL_PC5   = 0x02,
    SMC2_PIP       = 0x03,
    SMC1           = 0x04,
    SPI            = 0x05,
    PARALLEL_PC6   = 0x06,
    TIMER_4        = 0x07,
    RESERVED_0     = 0X08,
    PARALLEL_PC7   = 0x09,
    PARALLEL_PC8   = 0x0A,
    PARALLEL_PC9   = 0x0B,
    TIMER_3        = 0x0C,
    RESERVED_1     = 0x0D,
    PARALLEL_PC10  = 0x0E,
    PARALLEL_PC11  = 0x0F,
    I2C            = 0x10,
    RISC_TIMER     = 0x11,
    TIMER_2        = 0x12,
    RESERVED_2     = 0x13,
    IDMA2          = 0x14,
    IDMA1          = 0x15,
    SDMA_BUS_ERROR = 0x16,
    PARALLEL_PC12  = 0x17,
    PARALLEL_PC13  = 0x18,
    TIMER_1        = 0x19,
    PARALLEL_PC14  = 0x1A,
    SCC4       = 0x1B,
    SCC3       = 0x1C,
    SCC2           = 0x1D,
    SCC1           = 0x1E,
    PARALLEL_PC15  = 0x1F,

    SIU_IRQ0       = 0x20,  //ISR dependency: Locate SIU on 16 byte boundary.
    SIU_LVL0       = 0x21,
    SIU_IRQ1       = 0x22,
    SIU_LVL1       = 0x23,
    SIU_IRQ2       = 0x24,  // RPXC: QSpan Error - HBB: Local_QSpan/ISA/PCI IRQs
    SIU_LVL2       = 0x25,
    SIU_IRQ3       = 0x26,  // RPXC: ISA/PCI IRQs - HBB: cPCI_QSpan/cPCI IRQs
    SIU_LVL3       = 0x27,
    SIU_IRQ4       = 0x28,
    SIU_LVL4       = 0x29,
    SIU_IRQ5       = 0x2A,
    SIU_LVL5       = 0x2B,
    SIU_IRQ6       = 0x2C,
    SIU_LVL6       = 0x2D,
    SIU_IRQ7       = 0x2E,
    SIU_LVL7       = 0x2F,

#if defined( RPCG_RPXC ) | defined( SDB_HBB )
//
// Begin ISA vectors on 16-byte boundary
//
// - Use ISA_INT0 for 8259 Master vector base
// - Use ISA_INT8 for 8259 Slave vector base
//
    ISA_INT0       = 0x30,
    ISA_INT1       = 0x31,  // PS/2 Keyboard
    ISA_INT2       = 0x32,  // Slave IRQ controller input
    ISA_INT3       = 0x33,
    ISA_INT4       = 0x34,
    ISA_INT5       = 0x35,
    ISA_INT6       = 0x36,
    ISA_INT7       = 0x37,

    ISA_INT8       = 0x38,
    ISA_INT9       = 0x39,
    ISA_INT10      = 0x3A,  // Local PCI INT A
    ISA_INT11      = 0x3B,  // Local PCI INT B
    ISA_INT12      = 0x3C,  // PS/2 Mouse
    ISA_INT13      = 0x3D,
    ISA_INT14      = 0x3E,  // Local PCI INT C
    ISA_INT15      = 0x3F,  // Local PCI INT D

#endif

#if defined( SDB_HBB )
//
// Begin cPCI vectors on 16-byte boundary
//
    CPCI_INT_NONE  = 0x40,  // NO IRQ
    CPCI_INT_A     = 0x41,
    CPCI_INT_B     = 0x42,
    CPCI_INT_C     = 0x43,
    CPCI_INT_D     = 0x44,
    CPCI_ENUM      = 0x45,

#endif

    NUMBER_OF_INT_TABLE_ENTRIES
}
MOTO_DEVICE_ID;


//
// Define boundaries of sections of Interrupt table
//

#define FIRST_CPM_DEVICE CPM_RESERVED
#define LAST_CPM_DEVICE  PARALLEL_PC15

#define FIRST_SIU_DEVICE SIU_IRQ0
#define LAST_SIU_DEVICE  SIU_LVL7

#if defined( RPCG_RPXC ) | defined( SDB_HBB )
#define FIRST_ISA_INTERRUPT ISA_INT0
#define LAST_ISA_INTERRUPT  ISA_INT15
#endif

#if defined( SDB_HBB )
#define FIRST_CPCI_INTERRUPT CPCI_INT_NONE
#define LAST_CPCI_INTERRUPT  CPCI_ENUM
#endif


/* Parallel port definitions. These are the four multiple-purpose registers
   shared between most of the device drivers. */

/* Par. A. */
#define PAR_PA15        0x0001      /* Address is 0x952. */
#define PAR_PA14        0x0002
#define PAR_PA13        0x0004
#define PAR_PA12        0x0008
#define PAR_PA11        0x0010
#define PAR_PA10        0x0020
#define PAR_PA09        0x0040
#define PAR_PA08        0x0080
#define PAR_PA07        0x0100
#define PAR_PA06        0x0200
#define PAR_PA05        0x0400
#define PAR_PA04        0x0800
#define PAR_PA03        0x1000
#define PAR_PA02        0x2000
#define PAR_PA01        0x4000
#define PAR_PA00        0x8000
/* Par. B. */
#define PAR_PB31        0x00000001      /* Address is 0xABC. */
#define PAR_PB30        0x00000002
#define PAR_PB29        0x00000004
#define PAR_PB28        0x00000008
#define PAR_PB27        0x00000010
#define PAR_PB26        0x00000020
#define PAR_PB25        0x00000040
#define PAR_PB24        0x00000080
#define PAR_PB23        0x00000100
#define PAR_PB22        0x00000200
#define PAR_PB21        0x00000400
#define PAR_PB20        0x00000800
#define PAR_PB19        0x00001000
#define PAR_PB18        0x00002000
#define PAR_PB17        0x00004000
#define PAR_PB16        0x00008000
#define PAR_PB15        0x00010000      /* Bits 0 - 13 are reserved.  */
#define PAR_PB14        0x00020000
/* Par. C. */
#define PAR_PC15        0x0001
#define PAR_PC14        0x0002
#define PAR_PC13        0x0004
#define PAR_PC12        0x0008
#define PAR_PC11        0x0010
#define PAR_PC10        0x0020
#define PAR_PC09        0x0040
#define PAR_PC08        0x0080
#define PAR_PC07        0x0100
#define PAR_PC06        0x0200
#define PAR_PC05        0x0400
#define PAR_PC04        0x0800
/* Internal baudrate generator selectors. */
#define USE_BRG1        0x0001
#define USE_BRG2        0x0002
#define USE_BRG3        0x0003
#define USE_BRG4        0x0004

/* The definition order of the SCC/SMC parameter blocks. */
#define SCC1_PARM       0
#define SCC2_PARM       1
#define SCC3_PARM       2
#define SCC4_PARM       3
#define SMC1_PARM       2
#define SMC2_PARM       3

/* The definition order of the SCC/SMC Register blocks. */
#define SCC1_REG       0
#define SCC2_REG       1
#define SCC3_REG       2
#define SCC4_REG       3
#define SMC1_REG       0
#define SMC2_REG       1

typedef struct _BufferDescriptor {
    volatile unsigned short bd_length;   /* Transfer length.  */
       #define BD_EMPTY            0x8000
       #define BD_RESERVED1        0x4000
       #define BD_WRAP             0x2000
       #define BD_INTERUPT         0x1000
       #define BD_CTRL_CHAR        0x0800
       #define BD_MULTIDROP_ADDR   0x0400
       #define BD_CONTINUOUS_MODE  0x0200
       #define BD_IDLES_RECEIVED   0x0100
       #define BD_ADDR_MATCH       0x0080
       #define BD_RESERVED2        0x0040
       #define BD_BREAK_RECEIVED   0x0020
       #define BD_FRAME_ERROR      0x0010
       #define BD_PARITY_ERROR     0x0008
       #define BD_RESERVED3        0x0004
       #define BD_OVERRUN          0x0002
       #define BD_CARRIER_DT_LOST  0x0001
    volatile unsigned short bd_status;   /* Control status.   */
    volatile unsigned char  *bd_addr;    /* Data buffer addr. */
} BufferDescriptor, BD;


typedef struct IdmaBufferDescriptor
{
    unsigned short fcr;         /* Dest and Source FCR        */
    unsigned short stat_ctrl;   /* status and control         */
    unsigned long  bd_length;   /* transfer length            */
    unsigned char* source_addr; /* buffer source address      */
    unsigned char* dest_addr;   /* buffer destination address */
}
IDMA_BD;



//
// Define I/O Control service codes.
//

typedef enum {
    // Reserved base for OEM's is 32768

    OEM_IOCTL_ALLOC_MEM = 32768,
    OEM_IOCTL_FREE_MEM,
    OEM_IOCTL_GET_IMMR,
    OEM_IOCTL_RD_MODIFY_WRT,
    OEM_IOCTL_READ_REGISTER,
    OEM_IOCTL_WRITE_REGISTER,
    OEM_IOCTL_ISSUE_CPM_CMD,
    OEM_IOCTL_BUSY_STALL,
    OEM_IOCTL_PROC_VERSION,
    OEM_IOCTL_DOWNLOAD_UCODE,
    OEM_IOCTL_START_RISC,
    OEM_IOCTL_SET_BAUD_RATE,
    OEM_IOCTL_I2C_READ,
    OEM_IOCTL_I2C_WRITE,
    OEM_IOCTL_CI_ALLOC,
    OEM_IOCTL_CI_FREE,
    OEM_IOCTL_SET_TUNEABLES,
    OEM_IOCTL_GET_TUNEABLES,
    OEM_IOCTL_OAL_TEST,
    OEM_IOCTL_OAL_INSTRUMENT,
    OEM_IOCTL_SET_PIT,
    OEM_IOCTL_GET_SPI_PRAM_OFFSET,
    OEM_IOCTL_GET_I2C_PRAM_OFFSET,
    OEM_IOCTL_GET_ETHERNET_ADDRESS,
    OEM_IOCTL_SET_CPU_PROCESSOR_TYPE,
    OEM_IOCTL_DVCM_ENABLED
} OEM_IOCTL_CODE;

#define NOTUSED     (0)

// ************************************************************
// Defines for OEM_IOCTL_ISSUE_CMD
// ************************************************************

//
// Define CPCR OPCODE's
//

#define INIT_RX_TX_PARAMS  (0 << 8)
#define INIT_RX_PARAMS     (1 << 8)
#define INIT_TX_PARAMS     (2 << 8)
#define ENTER_HUNT_MODE    (3 << 8)
#define STOP_TX            (4 << 8)
#define GRACEFUL_STOP_TX   (5 << 8)
#define INIT_IDMA          (5 << 8)
#define RESTART_TX         (6 << 8)
#define CLOSE_RX_BD        (7 << 8)
#define SET_GROUP_ADDRESS  (8 << 8)
#define SET_TIMER          (8 << 8)
#define GCI_TIMEOUT        (9 << 8)
#define RESET_BCS         (10 << 8)
#define GCI_ABORT_REQUEST (10 << 8)
#define STOP_IDMA         (11 << 8)
#define START_DSP         (12 << 8)
#define INIT_DSP          (13 << 8)

//
// Define CPCR register channel numbers
//

#define SCC1_CH_NUM         (0 << 4)
#define I2C_CH_NUM          (1 << 4)
#define IDMA1_CH_NUM        (1 << 4)
#define SCC2_CH_NUM         (4 << 4)
#define SPI_CH_NUM          (5 << 4)
#define IDMA2_CH_NUM        (5 << 4)
#define RISC_TIMERS_CH_NUM  (5 << 4)
#define SCC3_CH_NUM         (8 << 4)
#define SMC1_CH_NUM         (9 << 4)
#define DSP1_CH_NUM         (9 << 4)
#define SCC4_CH_NUM         (12 << 4)
#define SMC2_CH_NUM        (13 << 4)
#define DSP2_CH_NUM        (13 << 4)


// ************************************************************
// Defines for OEM_IOCTL_ALLOC_MEM
// ************************************************************

//
// Allocation request structure
//

typedef struct {
    unsigned char  MemoryType;
    unsigned short NumberOfBytes;
} OEM_IOCTL_INT_MEM_REQUEST, *pOEM_IOCTL_INT_MEM_REQUEST;

//
// Define MemoryType.
//

#define MEMORY_BD    1
#define MEMORY_DATA  2
#define MEMORY_UCODE 3

// ************************************************************
// Defines for OEM_IOCTL_ALLOC_CI_MEM
// ************************************************************

//
// Allocation request structure
//

typedef struct {
    unsigned long NumberOfBytes;
    unsigned long Alignment;
} OEM_IOCTL_CI_MEM_REQUEST, *pOEM_IOCTL_CI_MEM_REQUEST;


// ************************************************************
// Defines for OEM_IOCTL_RD_MODIFY_WRT
// ************************************************************

typedef struct {
    PVOID Address;
    DWORD Size;
    DWORD AndMask;
    DWORD OrMask;
} RMW_OP, *pRMW_OP;


// ************************************************************
// Defines for OEM_IOCTL_WRITE_REGISTER
// ************************************************************

typedef struct {
    PVOID Address;
    DWORD Size;
    DWORD Data;
} WRITE_OP, *pWRITE_OP;


// ************************************************************
// Defines for OEM_IOCTL_READ_REGISTER
// ************************************************************

typedef struct {
    PVOID Address;
    DWORD Size;
} READ_OP, *pREAD_OP;


// ************************************************************
// Defines for OEM_IOCTL_GET_IMMR
// ************************************************************


typedef struct {
    PVOID PhysicalAddress;
    PVOID VirtualAddress;
} ADDRESSES, *pADDRESSES;


// ************************************************************
// Defines for OEM_IOCTL_PROC_VERSION
// ************************************************************

typedef struct {
    union {
        unsigned long AsUlong;
        struct {
            unsigned short Revision;
            unsigned short Version;
        } AsFields;
    } Pvr;
    unsigned short MicroCodeRevision;
    union {
        unsigned short AsUshort;
        struct {
            unsigned char  Masknum;
            unsigned char  Partnum;
        } AsFields;
    } Immr;
} PROC_DATA, *pPROC_DATA;


// ************************************************************
// Defines for OEM_IOCTL_SET_BAUD_RATE
// ************************************************************

//
// Action definitions:
//     the default value is 0 and means Allocate, SetBaudRate, Enable.
//

#define  NEW_BRG           0x0000
#define  MODIFY_BRG        0x0001   // Set if Generator field good
#define  ACQUIRE_BRG       0x0010   // Want cited Generator assigned

#define  SET_BAUD_RATE     0x0000
#define  SET_AUTOBAUD      0x0002
#define  NO_BAUD_RATE      0x0020   // Used only with ACQUIRE_BRG

#define  ENABLE_BRG        0x0000
#define  DISABLE_BRG       0x0004

#define  FREE_BRG          0x0008

typedef struct {
    unsigned long      Action;
    unsigned long      BaudRate;
    unsigned long      Multiplier;  // For SMCx, 16; else see pg 16-142.
    unsigned long      Generator;   // Previously allocated index.
    MOTO_DEVICE_ID     Device;      // Always required to be set.
} BAUD_RATE_DATA, *pBAUD_RATE_DATA;

#endif // #ifndef ASM_ONLY


//
// Translations between virtual and physical address ranges for 
// CacheInhibited space.
//
// Define hard coded physical to virtual translation for
// access to cache inhibited space (also called the internal
// memory map).
//

#define CACHE_INHIBITED_VIRTUAL_BASE 0xA0000000

#ifndef ASM_ONLY

#define VTOP(addr)  (((unsigned long)(addr)) & ~CACHE_INHIBITED_VIRTUAL_BASE)
#define PTOV(addr)  (((unsigned long)(addr)) |  CACHE_INHIBITED_VIRTUAL_BASE)

#endif // #ifndef ASM_ONLY


#endif // #ifndef _DD_SERV_H