firregs.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*

  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.

	Module Name:

		firregs.h

	Revision History:

		26th May   1999		Released

*/

#ifndef __FIRREGS_H__
#define __FIRREGS_H__

#ifdef __cplusplus
extern "C" {
#endif

/******************************************************************************
 * Modification Done by Maneesh Gupta
 *
 * S1.h has been replaced by platform.h 
 *****************************************************************************/
//#include "platform.h"
/******************************************************************************
 * End of modification Done by Maneesh Gupta
 *****************************************************************************/
#include "cc.h"

/* @field Start */
//PUCHAR		pBaseAddressDMAC;	//  DMA Controller registers
PUCHAR		pBaseAddressPMSC;	//  Power Management and System Configuration registers
PUCHAR		pBaseAddressFIR;	//  FIR Controller registers
PUCHAR		pBaseAddressGPIO;	//  GPIO registers




#define	INTC_ALLOCATE_SIZE	0x0100	
PUCHAR		pBaseAddressINTC;		
volatile PUSHORT pNIRR;				
volatile PUSHORT pNIMR;				


#ifdef OUTMSG

/* Some Registers for dump */
typedef struct DebugRegisters {
//---------INTC---------
    USHORT	NIMR;
//---------PMSC---------
	USHORT	SMSCR;
	USHORT 	SCONFR;
	USHORT 	SPLLCR;
	USHORT 	SRR;
//--------UART Register of FIR Portion----------
	UCHAR 	IrIER;
	UCHAR 	IrIIR;
	UCHAR 	IrLCR;
	UCHAR 	IrMCR;
//---------FIR Controller Register---------
	UCHAR 	ISIRR;
	UCHAR 	IFIRCR;
	UCHAR 	ITMCR;
//---------BANK0---------
	UCHAR 	IMSTCR;
	UCHAR 	ITC1R;
	UCHAR 	ITC2R;
	UCHAR 	IRCR;
//---------BANK1---------
	UCHAR 	IFAR;
	UCHAR 	IRBCLR;
	UCHAR 	IRBCHR;
	UCHAR 	IRRFPLR;
	UCHAR 	IRRFPHR;
	UCHAR 	ITBCLR;
	UCHAR 	ITBCHR;
//---------BANK2---------
	UCHAR 	IIRC1R;
	UCHAR 	IIRTCR;
	UCHAR 	IIRC2R;
	UCHAR 	ITMR;
	UCHAR 	IIRC3R;
//---------DMAC---------
//	ULONG	SAR0;
//	ULONG	DAR0;
//	ULONG	DMATCR0;
//	ULONG	CHCR0;
//	ULONG	DMAOR;
} DebugRegisters;

DebugRegisters dbgRegs;

#endif

/*********** DMA Controller Register ***********/
/* Variable 
volatile PULONG pSAR0;
volatile PULONG pDAR0;
volatile PULONG pDMATCR0;
volatile PULONG pCHCR0;
volatile PULONG pDMAOR;
*/

/***** Power Management and System Configuration register *****/
#define	PMSC_ALLOCATE_SIZE	0x12

/* Variable */
volatile PUSHORT pSMSCR;
volatile PUSHORT pSCONFR;
volatile PUSHORT pSBCR;
volatile PUSHORT pSPCCR;
volatile PUSHORT pSPSRCR;
volatile PUSHORT pSPLLCR;
volatile PUSHORT pSRR;
volatile PUSHORT pSTMCR;
volatile PUSHORT pSDIDR;

/*********** FIR Controller Register ***********/
#define	FIR_ALLOCATE_SIZE	0x0200
/*** Variable ***/
/* Bank0 */
volatile PUCHAR pIMSTCR;
volatile PUCHAR pIMSTSR;
volatile PUCHAR pIMISCR;
volatile PUCHAR pIRFR;
volatile PUCHAR pITFR;
volatile PUCHAR pITC1R;
volatile PUCHAR pITC2R;
volatile PUCHAR pITSR;
volatile PUCHAR pIRCR;
volatile PUCHAR pIRSR;
volatile PUCHAR pIRSTCR;
/* Bank1 */
volatile PUCHAR pIFAR;
volatile PUCHAR pIRBCLR;
volatile PUCHAR pIRBCHR;
volatile PUCHAR pIRRFPLR;
volatile PUCHAR pIRRFPHR;
volatile PUCHAR pITBCLR;
volatile PUCHAR pITBCHR;
/* Bank2 */
volatile PUCHAR pIIRC1R;
volatile PUCHAR pIIRTCR;
volatile PUCHAR pIIRC2R;
volatile PUCHAR pITMR;
volatile PUCHAR pIIRC3R;
/* BankX */
volatile PUCHAR pDMARP;
volatile PUCHAR pDMAWP;
volatile PUCHAR pISIRR;
volatile PUCHAR pIFIRCR;
volatile PUCHAR pITMCR;

/*********** UART Register of FIR Portion ***********/
/*** Variable ***/
volatile PUCHAR pIrRBR;
volatile PUCHAR pIrTBR;
volatile PUCHAR pIrIER;
volatile PUCHAR pIrIIR;
volatile PUCHAR pIrFCR;
volatile PUCHAR pIrLCR;
volatile PUCHAR pIrMCR;
volatile PUCHAR pIrDLL;
volatile PUCHAR pIrDLM;
volatile PUCHAR pIrLSR;
volatile PUCHAR pIrMSR;
volatile PUCHAR pIrSCR;

/*********** GPIO Register ***********/
/* Variable */
volatile PUSHORT pGPDCR;
volatile PUSHORT pGPDDR;



#ifdef __cplusplus
}
#endif


#endif __FIRREGS_H__