📄 init.c
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/*
Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
Module Name:
init.c
Revision History:
26th May 1999 Released
*/
#include "nsc.h"
#include "newdong.h"
#include "firregs.h"
/******************************************************************************
* Modification Done by Maneesh Gupta
*
* S1.h has been replaced by platform.h
*****************************************************************************/
//#include "platform.h"
/******************************************************************************
* End of modification Done by Maneesh Gupta
*****************************************************************************/
#include "cc.h"
#include "Settings.h"
#include "hw16550.h"
DongleParam *IrDongle;
UIR IrDongleResource;
#define SIR 0
#define MIR 1
#define FIR 2
extern UINT rcvDMAchannel;
extern UINT xmitDMAchannel;
#define NSC_DEMO_IRDA_SPEEDS ( NDIS_IRDA_SPEED_2400 | \
NDIS_IRDA_SPEED_2400 | \
NDIS_IRDA_SPEED_9600 | \
NDIS_IRDA_SPEED_19200 | \
NDIS_IRDA_SPEED_38400 | \
NDIS_IRDA_SPEED_57600 | \
NDIS_IRDA_SPEED_115200 | \
NDIS_IRDA_SPEED_1152K | \
NDIS_IRDA_SPEED_4M )
// NSC PC87108 index registers. See the spec for more info.
//
enum indexRegs {
BAIC_REG = 0,
CSRT_REG = 1,
MCTL_REG = 2,
GPDIR_REG = 3,
GPDAT_REG = 4
};
const UCHAR bankCode[] = { 0x03, 0x08, 0xE0, 0xE4, 0xE8, 0xEC, 0xF0, 0xF4};
//////////////////////////////////////////////////////////////////////////
// //
// Function : NSC_WriteBankReg //
// //
// Description: //
// Write a value to the specified register of the specified register //
// bank. //
// //
//////////////////////////////////////////////////////////////////////////
void NSC_WriteBankReg(UINT comBase, UINT bankNum, UINT regNum, UCHAR val)
{
NdisRawWritePortUchar(comBase+3, bankCode[bankNum]);
NdisRawWritePortUchar(comBase+regNum, val);
// Always switch back to reg 0
NdisRawWritePortUchar(comBase+3, bankCode[0]);
}
//////////////////////////////////////////////////////////////////////////
// //
// Function : NSC_ReadBankReg //
// //
// Description: //
// Write the value from the specified register of the specified //
// register bank. //
// //
//////////////////////////////////////////////////////////////////////////
UCHAR NSC_ReadBankReg(UINT comBase, UINT bankNum, UINT regNum)
{
UCHAR result;
NdisRawWritePortUchar(comBase+3, bankCode[bankNum]);
NdisRawReadPortUchar(comBase+regNum, &result);
// Always switch back to reg 0
NdisRawWritePortUchar(comBase+3, bankCode[0]);
return result;
}
//////////////////////////////////////////////////////////////////////////
// //
// Function : Ir108ConfigWrite //
// //
// Description: //
// Write the data in the indexed register of the configuration I/O. //
// //
//////////////////////////////////////////////////////////////////////////
void Ir108ConfigWrite(UINT configIOBase, UCHAR indexReg, UCHAR data)
{
#ifdef UNDER_CE
UCHAR IndexStore;
NdisRawReadPortUchar(configIOBase, &IndexStore);
Sleep(0);
NdisRawWritePortUchar(configIOBase, indexReg);
Sleep(0);
NdisRawWritePortUchar(configIOBase+1, data);
Sleep(0);
NdisRawWritePortUchar(configIOBase+1, data);
Sleep(0);
NdisRawWritePortUchar(configIOBase, IndexStore);
#else // UNDER_CE
UCHAR IndexStore;
NdisRawReadPortUchar(configIOBase, &IndexStore);
NdisRawWritePortUchar(configIOBase, indexReg);
NdisRawWritePortUchar(configIOBase+1, data);
NdisRawWritePortUchar(configIOBase+1, data);
NdisRawWritePortUchar(configIOBase, IndexStore);
#endif // !UNDER_CE
}
//////////////////////////////////////////////////////////////////////////
// //
// Function : Ir108ConfigRead //
// //
// Description: //
// Read the data in the indexed register of the configuration I/O. //
// //
//////////////////////////////////////////////////////////////////////////
UCHAR Ir108ConfigRead(UINT configIOBase, UCHAR indexReg)
{
UCHAR data,IndexStore;
NdisRawReadPortUchar(configIOBase, &IndexStore);
NdisRawWritePortUchar(configIOBase, indexReg);
NdisRawReadPortUchar(configIOBase+1, &data);
NdisRawWritePortUchar(configIOBase, IndexStore);
return (data);
}
#ifndef UNDER_CE
//////////////////////////////////////////////////////////////////////////
// //
// Function : PCIConfig560WriteWord //
// //
// Description: //
// Write a word to the PCI configuration space for PC87560. //
// //
//////////////////////////////////////////////////////////////////////////
VOID PCIConfig560WriteWord(UINT pciCfgAdr, UCHAR RegisterNumber, UINT data)
{
ULONG ConfigAddressIndex;
ConfigAddressIndex = (0x80002900| (ULONG)RegisterNumber);
NdisRawWritePortUlong(pciCfgAdr,
ConfigAddressIndex);
NdisRawWritePortUshort(pciCfgAdr+4, data);
}
#endif // !UNDER_CE
//////////////////////////////////////////////////////////////////////////
// //
// Function : NSC_DEMO_Init //
// //
// Description: //
// Set up configuration registers for NSC evaluation board. //
// //
// NOTE: //
// Assumes configuration registers are at I/O addr 0x398. //
// This function configures the demo board to make the SIR UART appear //
// at <comBase>. //
// //
// Called By: //
// OpenCom //
//////////////////////////////////////////////////////////////////////////
BOOLEAN NSC_DEMO_Init(IrDevice *thisDev)
{
DEBUGMSG(ZONE_FIRMODE, (TEXT("NSC_DEMO_Init -->\r\n")));
thisDev->portInfo.hwCaps.supportedSpeedsMask = NSC_DEMO_IRDA_SPEEDS;
thisDev->portInfo.hwCaps.turnAroundTime_usec = DEFAULT_TURNAROUND_usec;
thisDev->portInfo.hwCaps.extraBOFsRequired = 0;
// CE only supports one dongle.
#ifndef UNDER_CE
// Initialize thedongle structure before calling
// GetDongleCapabilities and SetDongleCapabilities for dongle 1.
//
thisDev->currentDongle = 1;
IrDongleResource.Signature =
thisDev->DongleTypes[thisDev->currentDongle];
IrDongleResource.ComPort = thisDev->portInfo.ioBase;
IrDongleResource.ModeReq = SIR;
IrDongleResource.XcvrNum = thisDev->currentDongle;
// IrDongle = GetDongleCapabilities(IrDongleResource);
IrDongle = NULL;
#endif // !UNDER_CE
// Initialize thedongle structure before calling
// GetDongleCapabilities and SetDongleCapabilities for dongle 0.
//
thisDev->currentDongle = 0;
IrDongleResource.Signature = thisDev->DongleTypes[thisDev->currentDongle];
IrDongleResource.ComPort = thisDev->portInfo.ioBase;
IrDongleResource.ModeReq = SIR;
IrDongleResource.XcvrNum = thisDev->currentDongle;
// IrDongle = GetDongleCapabilities(IrDongleResource);
// SetDongleCapabilities(IrDongleResource);
IrDongle = NULL;
DEBUGMSG(ZONE_FIRMODE, (TEXT("NSC_DEMO_Init <--\r\n")));
return TRUE;
}
//////////////////////////////////////////////////////////////////////////
// //
// Function: NSC_DEMO_Deinit //
// //
// DUMMY ROUTINE //
//////////////////////////////////////////////////////////////////////////
VOID NSC_DEMO_Deinit(UINT comBase, UINT context)
{
}
//////////////////////////////////////////////////////////////////////////
// //
// Function: NSC_DEMO_SetSpeed //
// //
// Description: //
// Set up the size of FCB, the timer, FIFO, DMA and the IR mode/dongle //
// speed based on the negotiated speed. //
// //
//////////////////////////////////////////////////////////////////////////
BOOLEAN NSC_DEMO_SetSpeed(
IrDevice *thisDev,
UINT comBase,
UINT bitsPerSec,
UINT context)
{
NDIS_STATUS stat;
UINT fcsSize;
UINT i;
DEBUGMSG(ZONE_FIRMODE, (TEXT("NSC_DEMO_SetSpeed -->\r\n")));
if (bitsPerSec > 115200) {
if(thisDev->currentSpeed <= MAX_SIR_SPEED){//change from SIR to FIR/MIR
if(READ_REGISTER_UCHAR(pISIRR) & CC_FIR_ISIRR_SIRMOD){
i=0;
while(i<10000){//Clean up UART Tx_FIFO
if((READ_REGISTER_UCHAR(pIrLSR) & (SERIAL_LSR_TEMT|SERIAL_LSR_THRE))==(SERIAL_LSR_TEMT|SERIAL_LSR_THRE)){
break;
}else{
}
i++;
}
i=0;
while(i<10000){//Clean up UART Rx_FIFO
if(READ_REGISTER_UCHAR(pIrLSR) & SERIAL_LSR_DR){
READ_REGISTER_UCHAR(pIrRBR);
}else{
break;
}
i++;
}
}else{//unexpected status
}
}else{//change from FIR/MIR to FIR/MIR
}
fcsSize = (bitsPerSec >= MIN_FIR_SPEED) ?
FAST_IR_FCS_SIZE : MEDIUM_IR_FCS_SIZE;
if(bitsPerSec >= MIN_FIR_SPEED){
IrDongleResource.ModeReq = FIR;
}
else
IrDongleResource.ModeReq = MIR;
// SetDongleCapabilities(IrDongleResource);
WRITE_REGISTER_UCHAR(pISIRR, 0x00);//4Mbps , 48MHz IRCLK
// Set MIR/FIR mode
//
WRITE_REGISTER_UCHAR(pIMSTCR,CC_FIR_IMSTCR_BANK2);//Switch Bank 2
switch( bitsPerSec){
case(4000000):
WRITE_REGISTER_UCHAR(pIIRC1R, CC_FIR_IIRC1R_IRMOD_FIR);
break;
case(1152000):
WRITE_REGISTER_UCHAR(pIIRC1R, CC_FIR_IIRC1R_IRSPD_1152|CC_FIR_IIRC1R_IRMOD_MIR);
break;
case(576000):
WRITE_REGISTER_UCHAR(pIIRC1R, CC_FIR_IIRC1R_IRSPD_0756|CC_FIR_IIRC1R_IRMOD_MIR);
break;
default : break;
}
//
// We may start receiving immediately so setup the
// receive DMA
//
// First, tear down any existing DMA
if (thisDev->AdapterState==ADAPTER_RX) {
NdisMCompleteDmaTransfer(&stat, thisDev->DmaHandle,
thisDev->rcvDmaBuffer,
thisDev->rcvDmaOffset,
thisDev->rcvDmaSize, FALSE);
}
WRITE_REGISTER_UCHAR(pIMSTCR,CC_FIR_IMSTCR_BANK0);//Switch Bank 0
i=0;
while(i<10000){//Clean up FIR Tx_FIFO
if(READ_REGISTER_UCHAR(pITSR) & CC_FIR_ITSR_EOM){
break;
}else{
}
i++;
}
i=0;
while(i<10000){//Clean up FIR Rx_FIFO
if(READ_REGISTER_UCHAR(pIRSR) & CC_FIR_IRSR_RFEM){
READ_REGISTER_UCHAR(pIRFR);
}else{
break;
}
i++;
}
#ifndef UNDER_CE
FindLargestSpace(thisDev, &thisDev->rcvDmaOffset, &thisDev->rcvDmaSize);
#endif //!UNDER_CE
SetupRecv(thisDev);
// Set the interrupt mask to interrupt on the
// first packet received.
//
thisDev->IntMask = 0x04;
}
else {
// Set SIR mode in UART before setting the timing of transciever
//
IrDongleResource.ModeReq = SIR;
}
LOG(TEXT("<==NSC_DEMO_SetSpeed"),0);
DEBUGMSG(ZONE_FIRMODE, (TEXT("NSC_DEMO_SetSpeed <--\r\n")));
return TRUE;
}
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