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WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

; Status Register (SR)

CC_CODEC_SR_IR71						.equ	h'4000
CC_CODEC_SR_TNF							.equ	h'2000

CC_CODEC_SR_TFS_E1E0					.equ	h'0000		; (FIFO-1, FIFO-0):(EMPTY,		EMPTY)
CC_CODEC_SR_TFS_E1N0					.equ	h'0800		; (FIFO-1, FIFO-0):(EMPTY,		NOT EMPTY)
CC_CODEC_SR_TFS_N1E0					.equ	h'1000		; (FIFO-1, FIFO-0):(NOT EMPTY,	EMPTY)
CC_CODEC_SR_TFS_N1N0					.equ	h'1800		; (FIFO-1, FIFO-0):(NOT EMPTY,	NOT EMPTY)

CC_CODEC_SR_TFU							.equ	h'0400
CC_CODEC_SR_TFO							.equ	h'0200
CC_CODEC_SR_TDI							.equ	h'0100
CC_CODEC_SR_RNE							.equ	h'0020

CC_CODEC_SR_RFS_N1N0					.equ	h'0000		; (FIFO-1, FIFO-0):(NOT FULL,	NOT FULL)
CC_CODEC_SR_RFS_N1F0					.equ	h'0008		; (FIFO-1, FIFO-0):(NOT FULL,	FULL)
CC_CODEC_SR_RFS_F1N0					.equ	h'0010		; (FIFO-1, FIFO-0):(FULL,		NOT FULL)
CC_CODEC_SR_RFS_F1F0					.equ	h'0018		; (FIFO-1, FIFO-0):(FULL,		FULL)

CC_CODEC_SR_RFU							.equ	h'0004
CC_CODEC_SR_RFO							.equ	h'0002
CC_CODEC_SR_RDI							.equ	h'0001

; Frequency Select Register (FSR)

CC_CODEC_FSR_FS_8000HZ					.equ	h'0000
CC_CODEC_FSR_FS_9600HZ					.equ	h'0001
CC_CODEC_FSR_FS_12000HZ					.equ	h'0002
CC_CODEC_FSR_FS_16000HZ					.equ	h'0003
CC_CODEC_FSR_FS_24000HZ					.equ	h'0004
CC_CODEC_FSR_FS_48000HZ					.equ	h'0005

; Command/Status Address Register (CAR/CSAR)

CC_CODEC_CAR_RW							.equ	h'00080000

; AC97 Transmit Interrupt Enable Register (ATIER)

CC_CODEC_ATIER_PLTFRQIE					.equ	h'20000000
CC_CODEC_ATIER_PRTFRQIE					.equ	h'10000000
CC_CODEC_ATIER_L1TFRQIE					.equ	h'08000000
CC_CODEC_ATIER_PCTFRQIE					.equ	h'04000000
CC_CODEC_ATIER_PLSTFRQIE				.equ	h'02000000
CC_CODEC_ATIER_PRSTFRQIE				.equ	h'01000000
CC_CODEC_ATIER_PLFETFRQIE				.equ	h'00800000
CC_CODEC_ATIER_L2TFRQIE					.equ	h'00400000
CC_CODEC_ATIER_HTTFRQIE					.equ	h'00200000
CC_CODEC_ATIER_IOCTFRQIE				.equ	h'00100000

CC_CODEC_ATIER_PLTFOVIE					.equ	h'00080000
CC_CODEC_ATIER_PRTFOVIE					.equ	h'00040000
CC_CODEC_ATIER_L1TFOVIE					.equ	h'00020000
CC_CODEC_ATIER_PCTFOVIE					.equ	h'00010000
CC_CODEC_ATIER_PLSTFOVIE				.equ	h'00008000
CC_CODEC_ATIER_PRSTFOVIE				.equ	h'00004000
CC_CODEC_ATIER_PLFETFOVIE				.equ	h'00002000
CC_CODEC_ATIER_L2TFOVIE					.equ	h'00001000
CC_CODEC_ATIER_HTTFOVIE					.equ	h'00000800
CC_CODEC_ATIER_IOCTFOVIE				.equ	h'00000400

CC_CODEC_ATIER_PLTFUNIE					.equ	h'00000200
CC_CODEC_ATIER_PRTFUNIE					.equ	h'00000100
CC_CODEC_ATIER_L1TFUNIE					.equ	h'00000080
CC_CODEC_ATIER_PCTFUNIE					.equ	h'00000040
CC_CODEC_ATIER_PLSTFUNIE				.equ	h'00000020
CC_CODEC_ATIER_PRSTFUNIE				.equ	h'00000010
CC_CODEC_ATIER_PLFETFUNIE				.equ	h'00000008
CC_CODEC_ATIER_L2TFUNIE					.equ	h'00000004
CC_CODEC_ATIER_HTTFUNIE					.equ	h'00000002
CC_CODEC_ATIER_IOCTFUNIE				.equ	h'00000001

; AC97 TX FIFO Status Register (ATSR)

CC_CODEC_ATSR_PLTFRQ					.equ	h'20000000
CC_CODEC_ATSR_PRTFRQ					.equ	h'10000000
CC_CODEC_ATSR_L1TFRQ					.equ	h'08000000
CC_CODEC_ATSR_PCTFRQ					.equ	h'04000000
CC_CODEC_ATSR_PLSTFRQ					.equ	h'02000000
CC_CODEC_ATSR_PRSTFRQ					.equ	h'01000000
CC_CODEC_ATSR_PLFETFRQ					.equ	h'00800000
CC_CODEC_ATSR_L2TFRQ					.equ	h'00400000
CC_CODEC_ATSR_HTTFRQ					.equ	h'00200000
CC_CODEC_ATSR_IOCTFRQ					.equ	h'00100000

CC_CODEC_ATSR_PLTFOV					.equ	h'00080000
CC_CODEC_ATSR_PRTFOV					.equ	h'00040000
CC_CODEC_ATSR_L1TFOV					.equ	h'00020000
CC_CODEC_ATSR_PCTFOV					.equ	h'00010000
CC_CODEC_ATSR_PLSTFOV					.equ	h'00008000
CC_CODEC_ATSR_PRSTFOV					.equ	h'00004000
CC_CODEC_ATSR_PLFETFOV					.equ	h'00002000
CC_CODEC_ATSR_L2TFOV					.equ	h'00001000
CC_CODEC_ATSR_HTTFOV					.equ	h'00000800
CC_CODEC_ATSR_IOCTFOV					.equ	h'00000400

CC_CODEC_ATSR_PLTFUN					.equ	h'00000200
CC_CODEC_ATSR_PRTFUN					.equ	h'00000100
CC_CODEC_ATSR_L1TFUN					.equ	h'00000080
CC_CODEC_ATSR_PCTFUN					.equ	h'00000040
CC_CODEC_ATSR_PLSTFUN					.equ	h'00000020
CC_CODEC_ATSR_PRSTFUN					.equ	h'00000010
CC_CODEC_ATSR_PLFETFUN					.equ	h'00000008
CC_CODEC_ATSR_L2TFUN					.equ	h'00000004
CC_CODEC_ATSR_HTTFUN					.equ	h'00000002
CC_CODEC_ATSR_IOCTFUN					.equ	h'00000001

; AC97 RX FIFO Interrupt Enable Register (ARIER)

CC_CODEC_ARIER_STARYIE					.equ	h'00400000
CC_CODEC_ARIER_STDRYIE					.equ	h'00200000

CC_CODEC_ARIER_PLRFRQIE					.equ	h'00100000
CC_CODEC_ARIER_PRRFRQIE					.equ	h'00080000
CC_CODEC_ARIER_L1RFRQIE					.equ	h'00040000
CC_CODEC_ARIER_MICRFRQIE				.equ	h'00020000
CC_CODEC_ARIER_L2RFRQIE					.equ	h'00010000
CC_CODEC_ARIER_HTRFRQIE					.equ	h'00008000
CC_CODEC_ARIER_IOCSRFRQIE				.equ	h'00004000

CC_CODEC_ARIER_PLRFOVIE					.equ	h'00002000
CC_CODEC_ARIER_PRRFOVIE					.equ	h'00001000
CC_CODEC_ARIER_L1RFOVIE					.equ	h'00000800
CC_CODEC_ARIER_MICRFOVIE				.equ	h'00000400
CC_CODEC_ARIER_L2RFOVIE					.equ	h'00000200
CC_CODEC_ARIER_HTRFOVIE					.equ	h'00000100
CC_CODEC_ARIER_IOCSRFOVIE				.equ	h'00000080

CC_CODEC_ARIER_PLRFUNIE					.equ	h'00000040
CC_CODEC_ARIER_PRRFUNIE					.equ	h'00000020
CC_CODEC_ARIER_L1RFUNIE					.equ	h'00000010
CC_CODEC_ARIER_MICRFUNIE				.equ	h'00000008
CC_CODEC_ARIER_L2RFUNIE					.equ	h'00000004
CC_CODEC_ARIER_HTRFUNIE					.equ	h'00000002
CC_CODEC_ARIER_IOCSRFUNIE				.equ	h'00000001

; AC97 RX FIFO Status Register (ARSR)

CC_CODEC_ARSR_STARY						.equ	h'00400000
CC_CODEC_ARSR_STDRY						.equ	h'00200000

CC_CODEC_ARSR_PLRFRQ					.equ	h'00100000
CC_CODEC_ARSR_PRRFRQ					.equ	h'00080000
CC_CODEC_ARSR_L1RFRQ					.equ	h'00040000
CC_CODEC_ARSR_MICRFRQ					.equ	h'00020000
CC_CODEC_ARSR_L2RFRQ					.equ	h'00010000
CC_CODEC_ARSR_HTRFRQ					.equ	h'00008000
CC_CODEC_ARSR_IOCSRFRQ					.equ	h'00004000

CC_CODEC_ARSR_PLRFOV					.equ	h'00002000
CC_CODEC_ARSR_PRRFOV					.equ	h'00001000
CC_CODEC_ARSR_L1RFOV					.equ	h'00000800
CC_CODEC_ARSR_MICRFOV					.equ	h'00000400
CC_CODEC_ARSR_L2RFOV					.equ	h'00000200
CC_CODEC_ARSR_HTRFOV					.equ	h'00000100
CC_CODEC_ARSR_IOCSRFOV					.equ	h'00000080

CC_CODEC_ARSR_PLRFUN					.equ	h'00000040
CC_CODEC_ARSR_PRRFUN					.equ	h'00000020
CC_CODEC_ARSR_L1RFUN					.equ	h'00000010
CC_CODEC_ARSR_MICRFUN					.equ	h'00000008
CC_CODEC_ARSR_L2RFUN					.equ	h'00000004
CC_CODEC_ARSR_HTRFUN					.equ	h'00000002
CC_CODEC_ARSR_IOCSRFUN					.equ	h'00000001

; AC97 Control Register (ACR)

CC_CODEC_ACR_VS							.equ	h'80000000
CC_CODEC_ACR_RXDMA_EN					.equ	h'00400000
CC_CODEC_ACR_TXDMA_EN					.equ	h'00200000
CC_CODEC_ACR_FCAF						.equ	h'00100000
CC_CODEC_ACR_FCDF						.equ	h'00080000
CC_CODEC_ACR_FSTAF						.equ	h'00040000
CC_CODEC_ACR_FSTDF						.equ	h'00020000
CC_CODEC_ACR_FPLTF						.equ	h'00010000
CC_CODEC_ACR_FPRTF						.equ	h'00008000
CC_CODEC_ACR_FL1TF						.equ	h'00004000
CC_CODEC_ACR_FPCTF						.equ	h'00002000
CC_CODEC_ACR_FPLSTF						.equ	h'00001000
CC_CODEC_ACR_FPRSTF						.equ	h'00000800
CC_CODEC_ACR_FPLETF						.equ	h'00000400
CC_CODEC_ACR_FL2TF						.equ	h'00000200
CC_CODEC_ACR_FHTF						.equ	h'00000100
CC_CODEC_ACR_FIOCTF						.equ	h'00000080
CC_CODEC_ACR_FPLRF						.equ	h'00000040
CC_CODEC_ACR_FPRRF						.equ	h'00000020
CC_CODEC_ACR_FL1RF						.equ	h'00000010
CC_CODEC_ACR_FMRF						.equ	h'00000008
CC_CODEC_ACR_FL2RF						.equ	h'00000004
CC_CODEC_ACR_FHRF						.equ	h'00000002
CC_CODEC_ACR_FIOSRF						.equ	h'00000001

;AC97 TAG Register (ATAGR)

CC_CODEC_ATAGR_CR						.equ	h'80000000

;Slot Request Active Register (SRAR)

CC_CODEC_SRAR_SL12RA					.equ	h'1000
CC_CODEC_SRAR_SL11RA					.equ	h'0800
CC_CODEC_SRAR_SL10RA					.equ	h'0400
CC_CODEC_SRAR_SL9RA						.equ	h'0200
CC_CODEC_SRAR_SL8RA						.equ	h'0100
CC_CODEC_SRAR_SL7RA						.equ	h'0080
CC_CODEC_SRAR_SL6RA						.equ	h'0040
CC_CODEC_SRAR_SL5RA						.equ	h'0020
CC_CODEC_SRAR_SL4RA						.equ	h'0010
CC_CODEC_SRAR_SL3RA						.equ	h'0008

;
; definitions for the Audio Front End on the companion chip (all the registers are 16 bits wide)
;

	.aif ENABLE_HD64464 eq h'00
CC_AFE_REGBASE_463						.equ	HD64463_BASE + HD64463_AFE_OFFSET
	.aendi
CC_AFE_REGBASE							.equ	HD64465_BASE + HD64465_AFE_OFFSET

CC_AFE_RXDB0_OFFSET						.equ	h'0000		; Receive buffer 0 
CC_AFE_RXDB1_OFFSET						.equ	h'0000		; Receive buffer 1 (same offset!) 
CC_AFE_TXDB0_OFFSET						.equ	h'0100		; Transmit buffer 0 
CC_AFE_TXDB1_OFFSET						.equ	h'0100		; Transmit buffer 1 (same offset!) 
CC_AFE_CTR_OFFSET						.equ	h'0200		; Control register 
CC_AFE_STR_OFFSET						.equ	h'0202		; Status register 
CC_AFE_RXDR_OFFSET						.equ	h'0204		; Receive data register 
CC_AFE_TXDR_OFFSET						.equ	h'0206		; Transmit data register 

CC_AFE_REGSIZE							.equ	h'0208		; total size of AFE registers 

CC_AFE_RXDB0							.equ	CC_AFE_REGBASE + CC_AFE_RXDB0_OFFSET	; Receive buffer 0 
CC_AFE_RXDB1							.equ	CC_AFE_REGBASE + CC_AFE_RXDB1_OFFSET	; Receive buffer 1 (same offset!) 
CC_AFE_TXDB0							.equ	CC_AFE_REGBASE + CC_AFE_TXDB0_OFFSET	; Transmit buffer 0 
CC_AFE_TXDB1							.equ	CC_AFE_REGBASE + CC_AFE_TXDB1_OFFSET	; Transmit buffer 1 (same offset!) 
CC_AFE_CTR								.equ	CC_AFE_REGBASE + CC_AFE_CTR_OFFSET		; Control register 
CC_AFE_STR								.equ	CC_AFE_REGBASE + CC_AFE_STR_OFFSET		; Status register 
CC_AFE_RXDR								.equ	CC_AFE_REGBASE + CC_AFE_RXDR_OFFSET		; Receive data register 
CC_AFE_TXDR								.equ	CC_AFE_REGBASE + CC_AFE_TXDR_OFFSET		; Transmit data register 

;
; definitions of DISPLAY interface (DSP) HD64463 BASE
;
	.aif ENABLE_HD64464 eq h'00
CC_DSP_REGBASE							.equ	HD64463_BASE + HD64463_LCDC_OFFSET

CC_DSP_LCDCBAR_OFFSET					.equ	h'0000		; Base Address Register Offset Address 
CC_DSP_LCDCLOR_OFFSET					.equ	h'0002		; Line address offset register  Offset Address
CC_DSP_LCDCCR_OFFSET					.equ	h'0004		; Control Register  Offset Address
CC_DSP_LDR1_OFFSET						.equ	h'0010		; LCD Display regsiter 1  Offset Address
CC_DSP_LDR2_OFFSET						.equ	h'0012		; LCD Display register 2  Offset Address
CC_DSP_LDHNCR_OFFSET					.equ	h'0014		; Num Chars in Horz. reg  Offset Address
CC_DSP_LDHNSR_OFFSET					.equ	h'0016		; Start Position of Horz. reg  Offset Address
CC_DSP_LDVNTR_OFFSET					.equ	h'0018		; Total Vertical Lines reg  Offset Address
CC_DSP_LDVNDR_OFFSET					.equ	h'001A		; Display Vertical Lines reg  Offset Address
CC_DSP_LDVSPR_OFFSET					.equ	h'001C		; Vertical Synchronous Pos. Reg  Offset Address
CC_DSP_LDR3_OFFSET						.equ	h'001E		; LCD Display register 3  Offset Address
CC_DSP_CRTVTR_OFFSET					.equ	h'0020		; CRT Vertical Total Register  Offset Address
CC_DSP_CRTVRSR_OFFSET					.equ	h'0022		; CRT Vertical Retrace Start Register  Offset Address
CC_DSP_CRTVRER_OFFSET					.equ	h'0024		; CRT Vertical Retrace End Register  Offset Address
CC_DSP_CPTWAR_OFFSET					.equ	h'0030		; Color Palette Write Addr Reg  Offset Address
CC_DSP_CPTWDR_OFFSET					.equ	h'0032		; Color Palette Write Data Reg  Offset Address
CC_DSP_CPTRAR_OFFSET					.equ	h'0034		; Color Palette Read Address Reg  Offset Address
CC_DSP_CPTRDR_OFFSET					.equ	h'0036		; Color Palette Read data reg  Offset Address

CC_DSP_REGSIZE							.equ	h'0038		; total size of DSP ASIC regs 

CC_DSP_LCDCBAR							.equ	CC_DSP_REGBASE + CC_DSP_LCDCBAR_OFFSET	; Base Address Register 
CC_DSP_LCDCLOR							.equ	CC_DSP_REGBASE + CC_DSP_LCDCLOR_OFFSET	; Line address offset register 
CC_DSP_LCDCCR							.equ	CC_DSP_REGBASE + CC_DSP_LCDCCR_OFFSET	; Control Register 
CC_DSP_LDR1								.equ	CC_DSP_REGBASE + CC_DSP_LDR1_OFFSET		; LCD Display regsiter 1 
CC_DSP_LDR2								.equ	CC_DSP_REGBASE + CC_DSP_LDR2_OFFSET		; LCD Display register 2 
CC_DSP_LDHNCR							.equ	CC_DSP_REGBASE + CC_DSP_LDHNCR_OFFSET	; Num Chars in Horz. reg 
CC_DSP_LDHNSR							.equ	CC_DSP_REGBASE + CC_DSP_LDHNSR_OFFSET	; Start Position of Horz. reg 
CC_DSP_LDVNTR							.equ	CC_DSP_REGBASE + CC_DSP_LDVNTR_OFFSET	; Total Vertical Lines reg 
CC_DSP_LDVNDR							.equ	CC_DSP_REGBASE + CC_DSP_LDVNDR_OFFSET	; Display Vertical Lines reg 
CC_DSP_LDVSPR							.equ	CC_DSP_REGBASE + CC_DSP_LDVSPR_OFFSET	; Vertical Synchronous Pos. Reg 
CC_DSP_LDR3								.equ	CC_DSP_REGBASE + CC_DSP_LDR3_OFFSET		; LCD Display register 3 
CC_DSP_CRTVTR							.equ	CC_DSP_REGBASE + CC_DSP_CRTVTR_OFFSET	; CRT Vertical Total Register 
CC_DSP_CRTVRSR							.equ	CC_DSP_REGBASE + CC_DSP_CRTVRSR_OFFSET	; CRT Vertical Retrace Start Register 
CC_DSP_CRTVRER							.equ	CC_DSP_REGBASE + CC_DSP_CRTVRER_OFFSET	; CRT Vertical Retrace End Register 
CC_DSP_CPTWAR							.equ	CC_DSP_REGBASE + CC_DSP_CPTWAR_OFFSET	; Color Palette Write Addr Reg 
CC_DSP_CPTWDR							.equ	CC_DSP_REGBASE + CC_DSP_CPTWDR_OFFSET	; Color Palette Write Data Reg 
CC_DSP_CPTRAR							.equ	CC_DSP_REGBASE + CC_DSP_CPTRAR_OFFSET	; Color Palette Read Address Reg 
CC_DSP_CPTRDR							.equ	CC_DSP_REGBASE + CC_DSP_CPTRDR_OFFSET	; Color Palette Read data reg 
	.aendi

	.aif ENABLE_HD64464 eq h'01
HD64464_OFFSET							.equ	h'03E00000
CC_DSP_REGBASE							.equ	(HD64464_BASE + HD64464_OFFSET)

CC_DSP_PM_OFFSET						.equ	h'00000000
CC_DSP_CC_OFFSET						.equ	h'00002000
CC_DSP_MM_OFFSET						.equ	h'00004000
CC_DSP_IN_OFFSET						.equ	h'00014000
CC_DSP_GC_OFFSET						.equ	h'0001E000
CC_DSP_GE_OFFSET						.equ	h'00020000
CC_DSP_FP_OFFSET						.equ	h'00022000
CC_DSP_CP1_OFFSET						.equ	h'00024000
CC_DSP_CP2_OFFSET						.equ	h'00026000
CC_DSP_CR_OFFSET						.equ	h'0002A000
CC_DSP_REGSIZE							.equ	h'00030000

CC_DSP_PM								.equ	(CC_DSP_REGBASE + CC_DSP_PM_OFFSET)	; Power Management + Clock Generation
CC_DSP_CC								.equ	(CC_DSP_REGBASE + CC_DSP_CC_OFFSET)	; CPU Interface
CC_DSP_MM								.equ	(CC_DSP_REGBASE + CC_DSP_MM_OFFSET)	; Memory Interface
CC_DSP_IN								.equ	(CC_DSP_REGBASE + CC_DSP_IN_OFFSET)	; Interrupt Controller
CC_DSP_GC								.equ	(CC_DSP_REGBASE + CC_DSP_GC_OFFSET)	; Graphics Controller 1 and 2
CC_DSP_GE								.equ	(CC_DSP_REGBASE + CC_DSP_GE_OFFSET)	; Graphics Engine
CC_DSP_FP								.equ	(CC_DSP_REGBASE + CC_DSP_FP_OFFSET)	; Flat Panel Controller
CC_DSP_CP1								.equ	(CC_DSP_REGBASE + CC_DSP_CP1_OFFSET); Color Palette 1
CC_DSP_CP2								.equ	(CC_DSP_REGBASE + CC_DSP_CP2_OFFSET); Color Palette 2
CC_DSP_CR								.equ	(CC_DSP_REGBASE + CC_DSP_CR_OFFSET)	; Configuration Registers
	.aendi

	.aif ENABLE_HD64464 eq h'01
CC_KBC_REGBASE							.equ	(HD64465_BASE + HD64465_KBC_OFFSET)

CC_KBC_CR_OFFSET						.equ	0x800
CC_KBC_SR_OFFSET						.equ	0x802

CC_KBC_CR								.equ	(CC_KBC_REGBASE + CC_KBC_CR_OFFSET)
CC_KBC_SR								.equ	(CC_KBC_REGBASE + CC_KBC_SR_OFFSET)
	.aendi