cc.inc

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

CC_FIR_IMSTCR_BANK2						.equ	0x02

;Master Status Register (IMSTSR)
CC_FIR_IMSTSR_TMI						.equ	0x40
CC_FIR_IMSTSR_TXI						.equ	0x20
CC_FIR_IMSTSR_RXI						.equ	0x10
CC_FIR_IMSTSR_IID_RXSC					.equ	0x08
CC_FIR_IMSTSR_IID_RXDA					.equ	0x0a
CC_FIR_IMSTSR_IID_TXBE					.equ	0x0c
CC_FIR_IMSTSR_IID_TXSC					.equ	0x0e

;Miscellaneous Control Register (IMISCR)
CC_FIR_IMISCR_DCS_TX					.equ	0x80
CC_FIR_IMISCR_DCS_RX					.equ	0x40
CC_FIR_IMISCR_DCS_NONE					.equ	0x00
CC_FIR_IMISCR_ILOOP						.equ	0x10

;Tx Control 1 Register(ITC1R)
CC_FIR_ITC1R_RTS						.equ	0x80
CC_FIR_ITC1R_TFRIEN						.equ	0x40
CC_FIR_ITC1R_TFUIEN						.equ	0x20
CC_FIR_ITC1R_TFTL						.equ	0x10
CC_FIR_ITC1R_ADRTS						.equ	0x08
CC_FIR_ITC1R_ACEOM						.equ	0x04
CC_FIR_ITC1R_TIDL						.equ	0x02
CC_FIR_ITC1R_UA							.equ	0x01

;Tx Control 2 Register (ITC2R)
CC_FIR_ITC2R_SB							.equ	0x80
CC_FIR_ITC2R_ACRCG						.equ	0x40
CC_FIR_ITC2R_SIP_NOW					.equ	0x20
CC_FIR_ITC2R_SIP_AFTER					.equ	0x10
CC_FIR_ITC2R_NSFP						.equ	0x08
CC_FIR_ITC2R_EEIL_EOM					.equ	0x00
CC_FIR_ITC2R_EEIL_16					.equ	0x01
CC_FIR_ITC2R_EEIL_32					.equ	0x02
CC_FIR_ITC2R_EEIL_64					.equ	0x03
CC_FIR_ITC2R_EEIL_128					.equ	0x04
CC_FIR_ITC2R_EEIL_256					.equ	0x05
CC_FIR_ITC2R_EEIL_512					.equ	0x06
CC_FIR_ITC2R_EEIL_1024					.equ	0x07

;Tx Status Register (ITSR)
CC_FIR_ITSR_TFUR						.equ	0x08
CC_FIR_ITSR_EOM							.equ	0x04
CC_FIR_ITSR_TFRDY						.equ	0x02
CC_FIR_ITSR_EEOM						.equ	0x01

;Rx Control Register (IRCR)
CC_FIR_IRCR_RFTL						.equ	0x80
CC_FIR_IRCR_ACRCC						.equ	0x40
CC_FIR_IRCR_RADM_ALL					.equ	0x00
CC_FIR_IRCR_RADM_LOHI_FAR				.equ	0x10
CC_FIR_IRCR_RADM_HI_FAR					.equ	0x20
CC_FIR_IRCR_SYNIEN						.equ	0x08
CC_FIR_IRCR_RFRIEN						.equ	0x02
CC_FIR_IRCR_SCIEN						.equ	0x01

;Rx Status Register (IRSR)
CC_FIR_IRSR_ABORT						.equ	0x80
CC_FIR_IRSR_CRCER						.equ	0x40
CC_FIR_IRSR_RFOVF						.equ	0x20
CC_FIR_IRSR_EOF							.equ	0x10
CC_FIR_IRSR_RFEM						.equ	0x08
CC_FIR_IRSR_SYNC						.equ	0x04

;Reset Command Register (IRSTCR)
CC_FIR_IRSTCR_RSTC_HUNT					.equ	0x10
CC_FIR_IRSTCR_RSTC_RXFIFO				.equ	0x20
CC_FIR_IRSTCR_RSTC_RXSCI				.equ	0x30
CC_FIR_IRSTCR_RSTC_RXRFP				.equ	0x40
CC_FIR_IRSTCR_RSTC_UNDERRUN				.equ	0x50
CC_FIR_IRSTCR_RSTC_TXFIFO				.equ	0x60
CC_FIR_IRSTCR_RSTC_HW					.equ	0x70

;Infrared Configuration 1 Register (IIRC1R)
CC_FIR_IIRC1R_IRSPD_1152				.equ	0x00
CC_FIR_IIRC1R_IRSPD_0756				.equ	0x10
CC_FIR_IIRC1R_IRSPD_0288				.equ	0x20
CC_FIR_IIRC1R_IRMOD_HPSIR				.equ	0x00
CC_FIR_IIRC1R_IRMOD_ASK					.equ	0x01
CC_FIR_IIRC1R_IRMOD_MIR					.equ	0x02
CC_FIR_IIRC1R_IRMOD_FIR					.equ	0x04

;Infrared Transceiver Control Register (IIRTCR)
CC_FIR_IIRTCR_DFREQ						.equ	0x20
CC_FIR_IIRTCR_MODSEL					.equ	0x10
CC_FIR_IIRTCR_ECHO						.equ	0x08
CC_FIR_IIRTCR_TXDF						.equ	0x02

;Infrared Configuration 2 Register (IIRC2R)
CC_FIR_IIRC2R_CHOP_DISABLE				.equ	0x70
CC_FIR_IIRC2R_CHOP_EX187				.equ	0x74
CC_FIR_IIRC2R_CHOP_EX229				.equ	0x78
CC_FIR_IIRC2R_CHOP_EX208				.equ	0x7c
CC_FIR_IIRC2R_CHOP_ENABLE_MAX			.equ	0xf0
CC_FIR_IIRC2R_CHOP_ENABLE_LESS			.equ	0xf4
CC_FIR_IIRC2R_CHOP_ENABLE_ZERO_BTB42	.equ	0xf8
CC_FIR_IIRC2R_CHOP_ENABLE_ZERO			.equ	0xfc
CC_FIR_IIRC2R_DSIRI						.equ	0x02
CC_FIR_IIRC2R_DFIRI						.equ	0x01

;Infrared Configuration 3 Register (IIRC3R)
CC_FIR_IIRC3R_SCDIEN					.equ	0x80
CC_FIR_IIRC3R_SCD						.equ	0x40
CC_FIR_IIRC3R_TMIEN						.equ	0x02
CC_FIR_IIRC3R_TMI						.equ	0x01

;SIR Register (ISIRR)
CC_FIR_ISIRR_SLOOP						.equ	0x02
CC_FIR_ISIRR_SIRMOD						.equ	0x01

;FIR Configuration Register (IFIRCR)
CC_FIR_IFIRCR_RX2_PP					.equ	0x04
CC_FIR_IFIRCR_RX_PP						.equ	0x02
CC_FIR_IFIRCR_TMODE						.equ	0x01

;Timing Control Register (ITMCR)
CC_FIR_ITMCR_TMCR_12					.equ	0x00
CC_FIR_ITMCR_TMCR_25					.equ	0x02
CC_FIR_ITMCR_TMCR_30					.equ	0x03
CC_FIR_ITMCR_TMCR_40					.equ	0x04
CC_FIR_ITMCR_TMCR_50					.equ	0x05
CC_FIR_ITMCR_TMCR_66					.equ	0x06


;
; definitions for the UART on the companion chip
;

CC_UART_REGBASE							.equ	HD64465_BASE + HD64465_UART_OFFSET

CC_UART_UTBR_OFFSET						.equ	0x0000
CC_UART_URBR_OFFSET						.equ	0x0000	// Mirrors UTBR
CC_UART_UIER_OFFSET						.equ	0x0002
CC_UART_UIIR_OFFSET						.equ	0x0004
CC_UART_UFCR_OFFSET						.equ	0x0004	// Mirrors UIIR
CC_UART_ULCR_OFFSET						.equ	0x0006
CC_UART_UMCR_OFFSET						.equ	0x0008
CC_UART_UDLL_OFFSET						.equ	0x0000
CC_UART_UDLM_OFFSET						.equ	0x0002
CC_UART_ULSR_OFFSET						.equ	0x000a
CC_UART_UMSR_OFFSET						.equ	0x000c
CC_UART_USCR_OFFSET						.equ	0x000e

CC_16550_REG_STRIDE						.equ	2				// each register is spaced 2 bytes apart

CC_UART_UTBR		.equ	(CC_UART_REGBASE + CC_UART_UTBR_OFFSET)
CC_UART_URBR		.equ	(CC_UART_REGBASE + CC_UART_URBR_OFFSET)
CC_UART_UIER		.equ	(CC_UART_REGBASE + CC_UART_UIER_OFFSET)
CC_UART_UIIR		.equ	(CC_UART_REGBASE + CC_UART_UIIR_OFFSET)
CC_UART_UFCR		.equ	(CC_UART_REGBASE + CC_UART_UFCR_OFFSET)
CC_UART_ULCR		.equ	(CC_UART_REGBASE + CC_UART_ULCR_OFFSET)
CC_UART_UMCR		.equ	(CC_UART_REGBASE + CC_UART_UMCR_OFFSET)
CC_UART_UDLL		.equ	(CC_UART_REGBASE + CC_UART_UDLL_OFFSET)
CC_UART_UDLM		.equ	(CC_UART_REGBASE + CC_UART_UDLM_OFFSET)
CC_UART_ULSR		.equ	(CC_UART_REGBASE + CC_UART_ULSR_OFFSET)
CC_UART_UMSR		.equ	(CC_UART_REGBASE + CC_UART_UMSR_OFFSET)
CC_UART_USCR		.equ	(CC_UART_REGBASE + CC_UART_USCR_OFFSET)

//
// Parallel Interface defines,  HD64465 only 99-08-11 cea
//

CC_PAR_BASE_REG 			.equ	(HD64465_BASE + HD64465_PARALLEL_OFFSET)
CC_PAR_DATA_REG 			.equ	CC_PAR_BASE_REG + 0x00
CC_PAR_STATUS_REG 			.equ	CC_PAR_BASE_REG + 0x02
CC_PAR_CONTROL_REG			.equ	CC_PAR_BASE_REG + 0x04
CC_PAR_ECP_DATA_REG			.equ	CC_PAR_BASE_REG + 0x10

CC_PAR_EXT_CONTROL_REG		.equ	CC_PAR_BASE_REG + 0x14

; CC_PAR_EXT_CONTROL_REG mode bits
; 		Bits 7-5 select mode,
;             000 = SPP
;             001 = PS/2 Parallel mode
;             010 = Parallel Port FIFO mode
;             011 = ECP Parallel Port mode
;             100 = Reserved
;             101 = Reserved
;             110 = Test mode
;             111 = Configuration mode
;		Bit 4 Error Interrupt Enable (nErrIntrEn) 0=enable, 1=disable
;		Bit 2 Service Interrupt (ServiceIntr) 0=enable, 1=disable
;
CC_PAR_SPP_MODE				.equ	(0x14)
CC_PAR_PS2_MODE				.equ	(0x34)
CC_PAR_ECP_MODE				.equ	(0x74)
CC_PAR_TEST_MODE			.equ	(0xC0)

; The WinCE documentation for the D9000
;   parallel port uses some variation in
;   the names of the parallel port bits.
;
;   The D9000 uses a 36 pin Centronics connector
;   on the debug interface board. This interface
;   seems to designed to look like a printer.
;
;   The S1 uses a 25 pin D-type connector. this
;   interface is designed to look like a host. To
;   make the S1 to behave like a printer is tricky.
;
;  DB25 (S1)                 Cen-36 (D9000)
;  DIR Pin#                  DIR Pin# 
;   O  1    CC_PAR_STROBE     I  1   DF_PAR_STROBE
;  I/O 2-9  (data bus)       I/O 2-9 (data bus)
;   I  10   CC_PAR_NACK       O  10  DF_PAR_NACK
;   I  11   CC_PAR_BUSY       O  11  DF_PAR_BUSY
;   I  12   CC_PAR_PE         O  12  DF_PAR_ERROR
;   I  13   CC_PAR_SELECT     O  13  DF_PAR_SELECT
;   O  14   CC_PAR_AUTOFD     I  14  DF_PAR_AUTOFD
;   I  15   CC_PAR_ERROR      O  32  DF_PAR_NFAULT
;   O  16   CC_PAR_INIT       I  31  DF_PAR_INIT
;   O  17   CC_PAR_SELECTIN   I  36  DF_PAR_SELECTIN
;
;           CC_PAR_READDIR       DF_PAR_EN
;           CC_PAR_IRQEN         DF_PAR_INTR_MASK
;
;--------------------------------------------------
;
;   The WinCE help data base describes a cable
;   to connect the development workstation to
;   a WinCE target. This is the cable used to 
;   connect to the HD64465 parallel port.
;
;

; CC_PAR_STATUS_REG bits
CC_PAR_BUSY					.equ	0x80
CC_PAR_NACK					.equ	0x40
CC_PAR_PE					.equ	0x20
CC_PAR_SELECT				.equ	0x10
CC_PAR_ERROR				.equ	0x08

; CC_PAR_CONTROL_REG bits
; 		CC_PAR_READDIR,0 = output, 1 = input
CC_PAR_READDIR				.equ	0x20
CC_PAR_IRQEN				.equ	0x10
CC_PAR_SELECTIN				.equ	0x08
CC_PAR_INIT					.equ	0x04
CC_PAR_AUTOFD				.equ	0x02
CC_PAR_STROBE				.equ	0x01

; CC_PAR_EXT_CONTROL_REG bits
CC_PAR_NERRINTRE			.equ	0x10
CC_PAR_SERVICEINTR			.equ	0x04
CC_PAR_OUT_FULL				.equ	0x02
CC_PAR_IN_EMPTY				.equ	0x01

;
; Serial CODEC Interface defines
;

	.aif ENABLE_HD64464 eq h'00
CC_CODEC_REGBASE_463					.equ	HD64463_BASE + HD64463_CODEC_OFFSET
	.aendi
CC_CODEC_REGBASE						.equ	HD64465_BASE + HD64465_CODEC_OFFSET
CC_CODEC_REGSIZE						.equ	h'0070

CC_CODEC_TDR_OFFSET						.equ	h'0000
CC_CODEC_RDR_OFFSET						.equ	h'0004
CC_CODEC_CR_OFFSET						.equ	h'0008
CC_CODEC_SR_OFFSET						.equ	h'000C
CC_CODEC_FSR_OFFSET						.equ	h'0010
CC_CODEC_CAR_OFFSET						.equ	h'0020
CC_CODEC_CDR_OFFSET						.equ	h'0024
CC_CODEC_PCML_OFFSET					.equ	h'0028
CC_CODEC_PCMR_OFFSET					.equ	h'002C
CC_CODEC_LINE1_OFFSET					.equ	h'0030
CC_CODEC_PCMC_OFFSET					.equ	h'0034
CC_CODEC_PCMLS_OFFSET					.equ	h'0038
CC_CODEC_PCMRS_OFFSET					.equ	h'003C
CC_CODEC_PCMLFE_OFFSET					.equ	h'0040
CC_CODEC_LINE2_OFFSET					.equ	h'0044
CC_CODEC_HSET_OFFSET					.equ	h'0048
CC_CODEC_IOCS_OFFSET					.equ	h'004C
CC_CODEC_ATIER_OFFSET					.equ	h'0050
CC_CODEC_ATSR_OFFSET					.equ	h'0054
CC_CODEC_ARIER_OFFSET					.equ	h'0058
CC_CODEC_ARSR_OFFSET					.equ	h'005C
CC_CODEC_ACR_OFFSET						.equ	h'0060
CC_CODEC_ATAGR_OFFSET					.equ	h'0064
CC_CODEC_SRAR_OFFSET					.equ	h'0068

CC_CODEC_TDR							.equ	CC_CODEC_REGBASE + CC_CODEC_TDR_OFFSET
CC_CODEC_RDR							.equ	CC_CODEC_REGBASE + CC_CODEC_RDR_OFFSET
CC_CODEC_CR								.equ	CC_CODEC_REGBASE + CC_CODEC_CR_OFFSET
CC_CODEC_SR								.equ	CC_CODEC_REGBASE + CC_CODEC_SR_OFFSET
CC_CODEC_FSR							.equ	CC_CODEC_REGBASE + CC_CODEC_FSR_OFFSET
CC_CODEC_CAR							.equ	CC_CODEC_REGBASE + CC_CODEC_CAR_OFFSET
CC_CODEC_CDR							.equ	CC_CODEC_REGBASE + CC_CODEC_CDR_OFFSET
CC_CODEC_PCML							.equ	CC_CODEC_REGBASE + CC_CODEC_PCML_OFFSET
CC_CODEC_PCMR							.equ	CC_CODEC_REGBASE + CC_CODEC_PCMR_OFFSET
CC_CODEC_LINE1							.equ	CC_CODEC_REGBASE + CC_CODEC_LINE1_OFFSET
CC_CODEC_PCMC							.equ	CC_CODEC_REGBASE + CC_CODEC_PCMC_OFFSET
CC_CODEC_PCMLS							.equ	CC_CODEC_REGBASE + CC_CODEC_PCMLS_OFFSET
CC_CODEC_PCMRS							.equ	CC_CODEC_REGBASE + CC_CODEC_PCMRS_OFFSET
CC_CODEC_PCMLFE							.equ	CC_CODEC_REGBASE + CC_CODEC_PCMLFE_OFFSET
CC_CODEC_LINE2							.equ	CC_CODEC_REGBASE + CC_CODEC_LINE2_OFFSET
CC_CODEC_HSET							.equ	CC_CODEC_REGBASE + CC_CODEC_HSET_OFFSET
CC_CODEC_IOCS							.equ	CC_CODEC_REGBASE + CC_CODEC_IOCS_OFFSET
CC_CODEC_ATIER							.equ	CC_CODEC_REGBASE + CC_CODEC_ATIER_OFFSET
CC_CODEC_ATSR							.equ	CC_CODEC_REGBASE + CC_CODEC_ATSR_OFFSET
CC_CODEC_ARIER							.equ	CC_CODEC_REGBASE + CC_CODEC_ARIER_OFFSET
CC_CODEC_ARSR							.equ	CC_CODEC_REGBASE + CC_CODEC_ARSR_OFFSET
CC_CODEC_ACR							.equ	CC_CODEC_REGBASE + CC_CODEC_ACR_OFFSET
CC_CODEC_ATAGR							.equ	CC_CODEC_REGBASE + CC_CODEC_ATAGR_OFFSET
CC_CODEC_SRAR							.equ	CC_CODEC_REGBASE + CC_CODEC_SRAR_OFFSET

; Control Register (CR)

CC_CODEC_CR_DMAEN						.equ	h'2000
CC_CODEC_CR_SL18						.equ	h'1000
CC_CODEC_CR_CDRT						.equ	h'0800
CC_CODEC_CR_WMRT						.equ	h'0400
CC_CODEC_CR_AC97S						.equ	h'0200
CC_CODEC_CR_SWR							.equ	h'0100
CC_CODEC_CR_PU							.equ	h'0080
CC_CODEC_CR_MS							.equ	h'0040
CC_CODEC_CR_ST							.equ	h'0020
CC_CODEC_CR_CRE							.equ	h'0010
CC_CODEC_CR_FTF							.equ	h'0008
CC_CODEC_CR_TXEN						.equ	h'0004
CC_CODEC_CR_FRF							.equ	h'0002
CC_CODEC_CR_RXEN						.equ	h'0001