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CC_INTC_NIMR_TMU0M_MASK .equ h'0400 ; TMU0M interrupt mask
CC_INTC_NIMR_TMU1M_MASK .equ h'0200 ; TMU1M interrupt mask
CC_INTC_NIMR_KBCM_MASK .equ h'0100 ; KBDM interrupt mask
CC_INTC_NIMR_IRDAM_MASK .equ h'0040 ; IRDAM interrupt mask
CC_INTC_NIMR_UART0M_MASK .equ h'0020 ; UART0M interrupt mask
CC_INTC_NIMR_UART1M_MASK .equ h'0010 ; UART1M interrupt mask
CC_INTC_NIMR_PPM_MASK .equ h'0008 ; PPM interrupt mask
CC_INTC_NIMR_SCDIM_MASK .equ h'0004 ; SCDIM interrupt mask
CC_INTC_NIMR_USBM_MASK .equ h'0002 ; USBM interrupt mask
CC_INTC_NIMR_ADCM_MASK .equ h'0001 ; ADCM interrupt mask
CC_INTC_NIMR_PS2KBM_UNMASK .equ 0x7FFF ; PS/2 Keyboard UNmask HD64465 only 99-08-11 cea
CC_INTC_NIMR_PS2MSM_UNMASK .equ 0xFF7F ; PS/2 mouse UNmask HD64465 only 99-08-11 cea
CC_INTC_NIMR_PCC0M_UNMASK .equ h'bfff ; PCC0M interrupt unmask
CC_INTC_NIMR_PCC1M_UNMASK .equ h'dfff ; PCC1M interrupt unmask
CC_INTC_NIMR_AFEM_UNMASK .equ h'efff ; AFEM interrupt unmask
CC_INTC_NIMR_GPIOM_UNMASK .equ h'f7ff ; GPIOM interrupt unmask
CC_INTC_NIMR_TMU0M_UNMASK .equ h'fbff ; TMU0M interrupt unmask
CC_INTC_NIMR_TMU1M_UNMASK .equ h'fdff ; TMU1M interrupt unmask
CC_INTC_NIMR_KBCM_UNMASK .equ h'feff ; KBDM interrupt unmask
CC_INTC_NIMR_IRDAM_UNMASK .equ h'ffbf ; IRDAM interrupt unmask
CC_INTC_NIMR_UART0M_UNMASK .equ h'ffdf ; UART0M interrupt unmask
CC_INTC_NIMR_UART1M_UNMASK .equ h'ffef ; UART1M interrupt unmask
CC_INTC_NIMR_PPM_UNMASK .equ h'fff7 ; PPM interrupt unmask
CC_INTC_NIMR_SCDIM_UNMASK .equ h'fffb ; SCDIM interrupt unmask
CC_INTC_NIMR_USBM_UNMASK .equ h'fffd ; USBM interrupt unmask
CC_INTC_NIMR_ADCM_UNMASK .equ h'fffe ; ADCM interrupt unmask
;
; definitions of Timer interface (TMR) on the companion chip
; all the timer registers are 16 bits wide
;
.aif ENABLE_HD64464 eq h'00
CC_TMR_REGBASE_463 .equ HD64463_BASE + HD64463_TMR_OFFSET
.aendi
CC_TMR_REGBASE .equ HD64465_BASE + HD64465_TMR_OFFSET
CC_TMR_TCVR1_OFFSET .equ h'0000 ; Constant 1 Offset Address
CC_TMR_TCVR0_OFFSET .equ h'0002 ; Constant 0 Offset Address
CC_TMR_TRVR1_OFFSET .equ h'0004 ; Read Count 1 Offset Address
CC_TMR_TRVR0_OFFSET .equ h'0006 ; Read Count 0 Offset Address
CC_TMR_TCR1_OFFSET .equ h'0008 ; Control 1 Offset Address
CC_TMR_TCR0_OFFSET .equ h'000A ; Control 0 Offset Address
CC_TMR_TIRR_OFFSET .equ h'000C ; Interrupt Request Offset Address
CC_TMR_TIDR_OFFSET .equ h'000E ; Interrupt Disable Offset Address
CC_TMR_REGSIZE .equ h'0010 ; total size of TMR regs in CC ASIC
CC_TMR_TCVR1 .equ CC_TMR_REGBASE + CC_TMR_TCVR1_OFFSET ; Constant 1
CC_TMR_TCVR0 .equ CC_TMR_REGBASE + CC_TMR_TCVR0_OFFSET ; Constant 0
CC_TMR_TRVR1 .equ CC_TMR_REGBASE + CC_TMR_TRVR1_OFFSET ; Read Count 1
CC_TMR_TRVR0 .equ CC_TMR_REGBASE + CC_TMR_TRVR0_OFFSET ; Read Count 0
CC_TMR_TCR1 .equ CC_TMR_REGBASE + CC_TMR_TCR1_OFFSET ; Control 1
CC_TMR_TCR0 .equ CC_TMR_REGBASE + CC_TMR_TCR0_OFFSET ; Control 0
CC_TMR_TIRR .equ CC_TMR_REGBASE + CC_TMR_TIRR_OFFSET ; Interrupt Request
CC_TMR_TIDR .equ CC_TMR_REGBASE + CC_TMR_TIDR_OFFSET ; Interrupt Mask
; Timer 1 Control Register (TCR1)
CC_TMR_TCR1_EDMA .equ h'0010
CC_TMR_TCR1_ETMO1 .equ h'0008
CC_TMR_TCR1_PST1_CKIO .equ h'0006
CC_TMR_TCR1_PST1_CKIO_DIVID_4 .equ h'0004
CC_TMR_TCR1_PST1_CKIO_DIVID_8 .equ h'0002
CC_TMR_TCR1_PST1_CKIO_DIVID_16 .equ h'0000
CC_TMR_TCR1_T1STP .equ h'0001
; Timer 0 Control Register (TCR1)
CC_TMR_TCR0_EADT .equ h'0010
CC_TMR_TCR0_ETMO0 .equ h'0008
CC_TMR_TCR0_PST0_CKIO .equ h'0006
CC_TMR_TCR0_PST0_CKIO_DIVID_4 .equ h'0004
CC_TMR_TCR0_PST0_CKIO_DIVID_8 .equ h'0002
CC_TMR_TCR0_PST0_CKIO_DIVID_16 .equ h'0000
CC_TMR_TCR0_T0STP .equ h'0001
; Timer Interrupt Request Register (TIRR)
CC_TMR_TIRR_TMU1R .equ h'0002
CC_TMR_TIRR_TMU0R .equ h'0001
; Timer Interrupt Disable Register (TIDR)
CC_TMR_TIRR_TMU1D .equ h'0002
CC_TMR_TIRR_TMU0D .equ h'0001
;
; PCMCIA defines
;
.aif ENABLE_HD64464 eq h'00
CC_PCMCIA_REGBASE_463 .equ HD64463_BASE + HD64463_PCMCIA_OFFSET
.aendi
CC_PCMCIA_REGBASE .equ HD64465_BASE + HD64465_PCMCIA_OFFSET
; Card 0 defines
CC_PCMCIA_PCC0ISR_OFFSET .equ h'0000 ; Interface Status Register offset address
CC_PCMCIA_PCC0GCR_OFFSET .equ h'0002 ; General Control Register offset address
CC_PCMCIA_PCC0CSCR_OFFSET .equ h'0004 ; Status Change Register offset address
CC_PCMCIA_PCC0CSCIER_OFFSET .equ h'0006 ; Status Change Int. En reg offset address
CC_PCMCIA_PCC0SCR_OFFSET .equ h'0008 ; Software Control reg offset address
CC_PCMCIA_PCCPSR_OFFSET .equ h'000a ; Serial Power Switch Control reg offset address
CC_PCMCIA_PCC0ISR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0ISR_OFFSET ; Interface Status Register
CC_PCMCIA_PCC0GCR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0GCR_OFFSET ; General Control Register
CC_PCMCIA_PCC0CSCR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0CSCR_OFFSET ; Status Change Register
CC_PCMCIA_PCC0CSCIER .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0CSCIER_OFFSET ; Status Change Int. En reg
CC_PCMCIA_PCC0SCR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0SCR_OFFSET ; Software Control reg
CC_PCMCIA_PCCPSR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCCPSR_OFFSET ; Serial Power Switch Control reg
; Card 1 defines
CC_PCMCIA_PCC1ISR_OFFSET .equ h'0010 ; Interface Status Register
CC_PCMCIA_PCC1GCR_OFFSET .equ h'0012 ; General Control Register
CC_PCMCIA_PCC1CSCR_OFFSET .equ h'0014 ; Status Change Register
CC_PCMCIA_PCC1CSCIER_OFFSET .equ h'0016 ; Status Change Int. En reg
CC_PCMCIA_PCC1SCR_OFFSET .equ h'0018 ; Software Control reg
CC_PCMCIA_PCC1ISR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1ISR_OFFSET ; Interface Status Register
CC_PCMCIA_PCC1GCR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1GCR_OFFSET ; General Control Register
CC_PCMCIA_PCC1CSCR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1CSCR_OFFSET ; Status Change Register
CC_PCMCIA_PCC1CSCIER .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1CSCIER_OFFSET ; Status Change Int. En reg
CC_PCMCIA_PCC1SCR .equ CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1SCR_OFFSET ; Software Control reg
CC_PCMCIA_REGSIZE .equ h'0020 ; as far as these regs can go
; Interface Status Reg
CC_PCMCIA_ISR_IREQ_MASK .equ h'80 ; mask to obtain value of IREQ pin
CC_PCMCIA_ISR_RDY_MASK .equ h'80 ; mask to obtain value of RDY pin
CC_PCMCIA_ISR_WP_MASK .equ h'40 ; mask to obtain value of WP pin
CC_PCMCIA_ISR_VS_MASK .equ h'30 ; mask to obtain value of VS1 and VS2
CC_PCMCIA_ISR_VS2_MASK .equ h'20 ; mask to obtain value of VS2
CC_PCMCIA_ISR_VS1_MASK .equ h'10 ; mask to obtain value of VS1
CC_PCMCIA_ISR_CD_MASK .equ h'0C ; mask to obtain value of CD1 and CD2
CC_PCMCIA_ISR_CD2_MASK .equ h'08 ; mask to obtain value of CD2
CC_PCMCIA_ISR_CD1_MASK .equ h'04 ; mask to obtain value of CD1
CC_PCMCIA_ISR_BVD_MASK .equ h'03 ; mask to obtain value of BVD pins
CC_PCMCIA_ISR_BVD_NORMAL .equ h'03 ; battery is fine
CC_PCMCIA_ISR_BVD_LOW_GD .equ h'01 ; battery is low but data is OK
CC_PCMCIA_ISR_BVD_LOW_CD .equ h'02 ; battery is low and data is corrupt
CC_PCMCIA_ISR_BVD_DEAD .equ h'00 ; battery is dead
CC_PCMCIA_ISR_SPKR_MASK .equ h'02 ; mask to obtain value of SPK pin
CC_PCMCIA_ISR_STSCH_MASK .equ h'01 ; mask to obtain value of STSCH pin
; General Control reg
CC_PCMCIA_GCR_DRV_ENABLE .equ h'80 ; Enables the PCMCIA card
CC_PCMCIA_GCR_RESET .equ h'40 ; Causes a reset on the card
CC_PCMCIA_GCR_IO_CARD .equ h'20 ; There is an I/O card in this slot
CC_PCMCIA_GCR_MEM_CARD .equ h'00 ; There is a mem card in this slot
CC_PCMCIA_GCR_5V_ENABLE .equ h'10 ; Spcifies to use 3.3V
CC_PCMCIA_GCR_MMOD_32 .equ h'00 ; set mode as 32MB mem areas
CC_PCMCIA_GCR_MMOD_16 .equ h'08 ; set mode as 16MB mem areas
CC_PCMCIA_GCR_A25_HIGH .equ h'04 ; set A25 High
CC_PCMCIA_GCR_A25_LOW .equ h'00 ; set A25 Low
CC_PCMCIA_GCR_A24_HIGH .equ h'02 ; set A24 High
CC_PCMCIA_GCR_A24_LOW .equ h'00 ; set A24 Low
CC_PCMCIA_GCR_ADDR_MASK .equ h'06 ; Mask A24 and A25
CC_PCMCIA_GCR_REG_HIGH .equ h'01 ; set REG High
CC_PCMCIA_GCR_REG_LOW .equ h'00 ; set REG Low
; Card Status Change (PCC0CSCR) Reg
CC_PCMCIA_CSCR_GEN_CD_INT .equ h'80 ; Generate a CD interrupt
CC_PCMCIA_CSCR_IREQ_INT_REQ .equ h'20 ; IREQ Int has occurred
CC_PCMCIA_CSCR_STSCH_INT_REQ .equ h'10 ; STSCH Int has occurred
CC_PCMCIA_CSCR_CD_INT_REQ .equ h'08 ; CD Int occurred
CC_PCMCIA_CSCR_RDY_INT_REQ .equ h'04 ; RDY Int occurred
CC_PCMCIA_CSCR_BW_INT_REQ .equ h'02 ; Batt warning int occurred
CC_PCMCIA_CSCR_BE_INT_REQ .equ h'01 ; Batt dead int occurred
CC_PCMCIA_CSCR_TPS2206_SEL .equ h'40 ; TPS2206 serial power switch
CC_PCMCIA_CSCR_MIC2563_SEL .equ h'bf ; MIC2563 select
; Card Status Change Interrupt Enable Reg
CC_PCMCIA_CSCIER_AUTO_GCR .equ h'80 ; Automatically init the GCR
CC_PCMCIA_CSCIER_IREQ_DIS .equ h'00 ; Disable IREQ ints
CC_PCMCIA_CSCIER_IREQ_LEVEL .equ h'20 ; IREQ Level ints
CC_PCMCIA_CSCIER_IREQ_PFE .equ h'40 ; IREQ Falling Edge, Pulse
CC_PCMCIA_CSCIER_IREQ_PRE .equ h'60 ; IREQ Rising Edge Pulse
CC_PCMCIA_CSCIER_IREQ_MASK .equ h'60 ; For masking this value
CC_PCMCIA_CSCIER_STSCH_INT_EN .equ h'10 ; Enable STSCH Interrupts
CC_PCMCIA_CSCIER_CD_INT_EN .equ h'08 ; Enable CD Interrupts
CC_PCMCIA_CSCIER_RDY_INT_EN .equ h'04 ; Enable RDY/BSY Interrupts
CC_PCMCIA_CSCIER_BWE_INT_EN .equ h'02 ; Enable Batt Warning Interrupts
CC_PCMCIA_CSCIER_BDE_INT_EN .equ h'01 ; Enable Batt Dead Interrupts
; Software control reg
CC_PCMCIA_SCR_3V_ENABLE .equ h'02 ; Specifies to use 5V
CC_PCMCIA_SCR_MASK_VCC .equ h'0c ; Masks out our bits
CC_PCMCIA_SCR_VCC0VPP0 .equ h'04 ; Voltage control pin P0VPP0
CC_PCMCIA_SCR_VCC0VPP1 .equ h'08 ; Voltage control pin P0VPP1
CC_PCMCIA_SCR_VCC1VPP0 .equ h'04 ; Voltage control pin P1VPP0
CC_PCMCIA_SCR_VCC1VPP1 .equ h'08 ; Voltage control pin P1VPP1
CC_PCMCIA_SCR_SHDN_ENB .equ h'10 ; Shutdown bit for TPS2206
; Serial Power Switch Control Register
CC_PCMCIA_PSR_5V_ENBB .equ h'80 ; Enable BVcc 5V
CC_PCMCIA_PSR_3V_ENBB .equ h'40 ; Enable BVcc 3.3V
CC_PCMCIA_PSR_BVPP_VCC .equ h'20 ; Enable BVpp 3.3V or 5V
CC_PCMCIA_PSR_BVPP_PGM .equ h'10 ; Enable BVpp 12v
CC_PCMCIA_PSR_3V_ENBA .equ h'08 ; Enable AVcc 3.3V
CC_PCMCIA_PSR_5V_ENBA .equ h'04 ; Enable AVcc 5V
CC_PCMCIA_PSR_AVPP_VCC .equ h'02 ; Enable AVpp 3.3V or 5V
CC_PCMCIA_PSR_AVPP_PGM .equ h'01 ; Enable AVpp 12V
CC_PCMCIA_PSR_AVCC_MASK .equ h'0c
CC_PCMCIA_PSR_AVPP_MASK .equ h'03
CC_PCMCIA_PSR_BVCC_MASK .equ h'c0
CC_PCMCIA_PSR_BVPP_MASK .equ h'30
CC_PCMCIA_PSR_AVCC_AVPP .equ CC_PCMCIA_PSR_AVCC_MASK | CC_PCMCIA_PSR_AVPP_MASK
CC_PCMCIA_PSR_BVCC_BVPP .equ CC_PCMCIA_PSR_BVCC_MASK | CC_PCMCIA_PSR_BVPP_MASK
;
; definitions for the FIR on the companion chip
;
CC_FIR_REGBASE .equ HD64465_BASE + HD64465_FIR_OFFSET
CC_FIR_IRRBR_OFFSET .equ 0x0000 ; Receiver Buffer Register offset address
CC_FIR_IRTBR_OFFSET .equ 0x0000 ; Transmitter Buffer Register offset address
CC_FIR_IRIER_OFFSET .equ 0x0002 ; Interrupt Enable Register offset address
CC_FIR_IRIIR_OFFSET .equ 0x0004 ; Interrupt Identification Register offset address
CC_FIR_IRFCR_OFFSET .equ 0x0004 ; FIFO Control Register offset address
CC_FIR_IRLCR_OFFSET .equ 0x0006 ; Line Control Register offset address
CC_FIR_IRMCR_OFFSET .equ 0x0008 ; Modem Control Register offset address
CC_FIR_IRDLL_OFFSET .equ 0x0000 ; Divisor Latch LSB offset address
CC_FIR_IRDLM_OFFSET .equ 0x0002 ; Divisor Latch MSB offset address
CC_FIR_IRLSR_OFFSET .equ 0x000a ; Line Status Register offset address
CC_FIR_IRMSR_OFFSET .equ 0x000c ; Modem Status Register offset address
CC_FIR_IRSCR_OFFSET .equ 0x000e ; Scratch Pad Register offset address
CC_FIR_IMSTCR_OFFSET .equ 0x0100 ; Master Control Register offset address
CC_FIR_IMSTSR_OFFSET .equ 0x0102 ; Master Status Register offset address
CC_FIR_IMISCR_OFFSET .equ 0x0102 ; Misc. Control Register offset address
CC_FIR_IRFR_OFFSET .equ 0x0104 ; Rx FIFO Register offset address
CC_FIR_ITFR_OFFSET .equ 0x0104 ; Tx FIFO Register offset address
CC_FIR_ITC1R_OFFSET .equ 0x0106 ; Tx Control 1 Register offset address
CC_FIR_ITC2R_OFFSET .equ 0x0108 ; Tx Control 2 Register offset address
CC_FIR_ITSR_OFFSET .equ 0x010a ; Tx Status Register offset address
CC_FIR_IRCR_OFFSET .equ 0x010c ; Rx control Register offset address
CC_FIR_IRSR_OFFSET .equ 0x010e ; Rx Status Register offset address
CC_FIR_IRSTCR_OFFSET .equ 0x010e ; Reset Command Register offset address
CC_FIR_IFAR_OFFSET .equ 0x0102 ; Frame Address Register offset address
CC_FIR_IRBCLR_OFFSET .equ 0x0104 ; Rx Byte Count Low Register offset address
CC_FIR_IRBCHR_OFFSET .equ 0x0106 ; Rx Byte Count High Register offset address
CC_FIR_IRRFPLR_OFFSET .equ 0x0108 ; Rx Ring Frame Pointer Low Register offset address
CC_FIR_IRRFPHR_OFFSET .equ 0x010a ; Rx Ring Frame Pointer High Register offset address
CC_FIR_ITBCLR_OFFSET .equ 0x010c ; Tx Byte Count Low Register offset address
CC_FIR_ITBCHR_OFFSET .equ 0x010e ; Tx Byte Count High Register offset address
CC_FIR_IIRC1R_OFFSET .equ 0x0102 ; Infrared Configuration 1 Register offset address
CC_FIR_IIRTCR_OFFSET .equ 0x0104 ; Infrared Transceiver Control Register offset address
CC_FIR_IIRC2R_OFFSET .equ 0x0106 ; Infrared Configuration 2 Register offset address
CC_FIR_ITMR_OFFSET .equ 0x0108 ; Timer Register offset address
CC_FIR_IIRC3R_OFFSET .equ 0x010a ; Infrared Configuration 3 Register offset address
CC_FIR_DMARP_OFFSET .equ 0x0110 ; DMA Data Read Port offset address
CC_FIR_DMAWP_OFFSET .equ 0x0110 ; DMA Data Write Port offset address
CC_FIR_ISIRR_OFFSET .equ 0x0120 ; SIR Register offset address
CC_FIR_IFIRCR_OFFSET .equ 0x01e0 ; FIR Configuration Register offset address
CC_FIR_ITMCR_OFFSET .equ 0x01f0 ; Timing Control Register offset address
CC_FIR_IRRBR .equ (CC_FIR_REGBASE + CC_FIR_IRRBR_OFFSET) ;Receiver Buffer Register
CC_FIR_IRTBR .equ (CC_FIR_REGBASE + CC_FIR_IRTBR_OFFSET) ;Transmitter Buffer Register
CC_FIR_IRIER .equ (CC_FIR_REGBASE + CC_FIR_IRIER_OFFSET) ;Interrupt Enable Register
CC_FIR_IRIIR .equ (CC_FIR_REGBASE + CC_FIR_IRIIR_OFFSET) ;Interrupt Identification Register
CC_FIR_IRFCR .equ (CC_FIR_REGBASE + CC_FIR_IRFCR_OFFSET) ;FIFO Control Register
CC_FIR_IRLCR .equ (CC_FIR_REGBASE + CC_FIR_IRLCR_OFFSET) ;Line Control Register
CC_FIR_IRMCR .equ (CC_FIR_REGBASE + CC_FIR_IRMCR_OFFSET) ;Modem Control Register
CC_FIR_IRDLL .equ (CC_FIR_REGBASE + CC_FIR_IRDLL_OFFSET) ;Divisor Latch LSB
CC_FIR_IRDLM .equ (CC_FIR_REGBASE + CC_FIR_IRDLM_OFFSET) ;Divisor Latch MSB
CC_FIR_IRLSR .equ (CC_FIR_REGBASE + CC_FIR_IRLSR_OFFSET) ;Line Status Register
CC_FIR_IRMSR .equ (CC_FIR_REGBASE + CC_FIR_IRMSR_OFFSET) ;Modem Status Register
CC_FIR_IRSCR .equ (CC_FIR_REGBASE + CC_FIR_IRSCR_OFFSET) ;Scratch Pad Register
CC_FIR_IMSTCR .equ (CC_FIR_REGBASE + CC_FIR_IMSTCR_OFFSET) ;Master Control Register
CC_FIR_IMSTSR .equ (CC_FIR_REGBASE + CC_FIR_IMSTSR_OFFSET) ;Master Status Register
CC_FIR_IMISCR .equ (CC_FIR_REGBASE + CC_FIR_IMISCR_OFFSET) ;Misc. Control Register
CC_FIR_IRFR .equ (CC_FIR_REGBASE + CC_FIR_IRFR_OFFSET) ;Rx FIFO Register
CC_FIR_ITFR .equ (CC_FIR_REGBASE + CC_FIR_ITFR_OFFSET) ;Tx FIFO Register
CC_FIR_ITC1R .equ (CC_FIR_REGBASE + CC_FIR_ITC1R_OFFSET) ;Tx Control 1 Register
CC_FIR_ITC2R .equ (CC_FIR_REGBASE + CC_FIR_ITC2R_OFFSET) ;Tx Control 2 Register
CC_FIR_ITSR .equ (CC_FIR_REGBASE + CC_FIR_ITSR_OFFSET) ;Tx Status Register
CC_FIR_IRCR .equ (CC_FIR_REGBASE + CC_FIR_IRCR_OFFSET) ;Rx control Register
CC_FIR_IRSR .equ (CC_FIR_REGBASE + CC_FIR_IRSR_OFFSET) ;Rx Status Register
CC_FIR_IRSTCR .equ (CC_FIR_REGBASE + CC_FIR_IRSTCR_OFFSET) ;Reset Command Register
CC_FIR_IFAR .equ (CC_FIR_REGBASE + CC_FIR_IFAR_OFFSET) ;Frame Address Register
CC_FIR_IRBCLR .equ (CC_FIR_REGBASE + CC_FIR_IRBCLR_OFFSET) ;Rx Byte Count Low Register
CC_FIR_IRBCHR .equ (CC_FIR_REGBASE + CC_FIR_IRBCHR_OFFSET) ;Rx Byte Count High Register
CC_FIR_IRRFPLR .equ (CC_FIR_REGBASE + CC_FIR_IRRFPLR_OFFSET);Rx Ring Frame Pointer Low Register
CC_FIR_IRRFPHR .equ (CC_FIR_REGBASE + CC_FIR_IRRFPHR_OFFSET);Rx Ring Frame Pointer High Register
CC_FIR_ITBCLR .equ (CC_FIR_REGBASE + CC_FIR_ITBCLR_OFFSET) ;Tx Byte Count Low Register
CC_FIR_ITBCHR .equ (CC_FIR_REGBASE + CC_FIR_ITBCHR_OFFSET) ;Tx Byte Count High Register
CC_FIR_IIRC1R .equ (CC_FIR_REGBASE + CC_FIR_IIRC1R_OFFSET) ;Infrared Configuration 1 Register
CC_FIR_IIRTCR .equ (CC_FIR_REGBASE + CC_FIR_IIRTCR_OFFSET) ;Infrared Transceiver Control Register
CC_FIR_IIRC2R .equ (CC_FIR_REGBASE + CC_FIR_IIRC2R_OFFSET) ;Infrared Configuration 2 Register
CC_FIR_ITMR .equ (CC_FIR_REGBASE + CC_FIR_ITMR_OFFSET) ;Timer Register
CC_FIR_IIRC3R .equ (CC_FIR_REGBASE + CC_FIR_IIRC3R_OFFSET) ;Infrared Configuration 3 Register
CC_FIR_DMARP .equ (CC_FIR_REGBASE + CC_FIR_DMARP_OFFSET) ;DMA Data Read Port
CC_FIR_DMAWP .equ (CC_FIR_REGBASE + CC_FIR_DMAWP_OFFSET) ;DMA Data Write Port
CC_FIR_ISIRR .equ (CC_FIR_REGBASE + CC_FIR_ISIRR_OFFSET) ;SIR Register
CC_FIR_IFIRCR .equ (CC_FIR_REGBASE + CC_FIR_IFIRCR_OFFSET) ;FIR Configuration Register
CC_FIR_ITMCR .equ (CC_FIR_REGBASE + CC_FIR_ITMCR_OFFSET) ;Timing Control Register
;Master Control Register (IMSTCR)
CC_FIR_IMSTCR_IEN .equ 0x80
CC_FIR_IMSTCR_TXEN .equ 0x40
CC_FIR_IMSTCR_RXEN .equ 0x20
CC_FIR_IMSTCR_RST_BANK .equ 0xe0
CC_FIR_IMSTCR_BANK0 .equ 0x00
CC_FIR_IMSTCR_BANK1 .equ 0x01
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