cc.inc

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

;
;  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
;
;	Module Name:
;
;		cc.inc
;
;	Revision History:
;
;		26th April 1999		Released
;		25th May   1999		Added FIR definitions
;		14th June  1999		Added HD64464's definitions
;		28th June  1999		Fixed minor bug
;


; Companion Chip (HD64465) module offsets

HD64465_STB_SYSTEM_OFFSET				.equ	h'0000		; Power down modes & system configuration
HD64465_RESERVED						.equ	h'1000		; Reserved
HD64465_PCMCIA_OFFSET					.equ	h'2000		; PCMCIA
HD64465_AFE_OFFSET						.equ	h'3000		; Modem analog front end
HD64465_GPIO_OFFSET						.equ	h'4000		; I/O ports
HD64465_INTC_OFFSET						.equ	h'5000		; Interrupt Controller
HD64465_TMR_OFFSET						.equ	h'6000		; Timer
HD64465_FIR_OFFSET						.equ	h'7000		; IrDA/16550(A) UART
HD64465_UART_OFFSET						.equ	h'8000		; 16550(B) UART
HD64465_EMBEDED_SDRAM_OFFSET			.equ	h'9000		; Embeded SDRAM
HD64465_PARALLEL_OFFSET					.equ	h'A000		; Parallel Port
HD64465_USB_OFFSET						.equ	h'B000		; USB Host Controller
HD64465_CODEC_OFFSET					.equ	h'C000		; Serial CODEC Interface
HD64465_KBC_OFFSET						.equ	h'D000		; Keyboard Controller Interface
HD64465_ADC_OFFSET						.equ	h'E000		; A/D Converter


; Companion Chip (HD64463) module offsets
	.aif ENABLE_HD64464 eq h'00
HD64463_STB_SYSTEM_OFFSET				.equ	h'0000		; Power down modes & system configuration 
HD64463_LCDC_OFFSET						.equ	h'1000		; LCD/CRT 
HD64463_PCMCIA_OFFSET					.equ	h'2000		; PCMCIA 
HD64463_AFE_OFFSET						.equ	h'3000		; Modem analog front end 
HD64463_GPIO_OFFSET						.equ	h'4000		; I/O ports 	
HD64463_INTC_OFFSET						.equ	h'5000		; Interrupt Controller 
HD64463_TMR_OFFSET						.equ	h'6000		; Timer 
HD64463_FIR_OFFSET						.equ	h'7000		; IrDA/16550(A) UART 
HD64463_UART0_OFFSET					.equ	h'8000		; 16550(B) UART  
HD64463_UART1_OFFSET					.equ	h'9000		; Embeded SDRAM 
HD64463_PARALLEL_OFFSET					.equ	h'A000		; Parallel Port 
HD64463_USB_OFFSET						.equ	h'B000		; USB Host Controller 
HD64463_CODEC_OFFSET					.equ	h'C000		; Serial CODEC Interface 
HD64463_KBC_OFFSET						.equ	h'D000		; Keyboard Controller Interface 
HD64463_ADC_OFFSET						.equ	h'E000		; A/D Converter 
	.aendi

;
; definitions of System control and power interface (SYS) on the companion chip ( all the system registers are 16 bits wide )
;

	.aif ENABLE_HD64464 eq h'00
CC_SYS_REGBASE_463						.equ	HD64463_BASE + HD64463_STB_SYSTEM_OFFSET
	.aendi
CC_SYS_REGBASE							.equ	HD64465_BASE + HD64465_STB_SYSTEM_OFFSET

CC_SYS_SMSCR_OFFSET						.equ	h'0000
CC_SYS_SCONFR_OFFSET					.equ	h'0002
CC_SYS_SBCR_OFFSET						.equ	h'0004
CC_SYS_SPCCR_OFFSET						.equ	h'0006
CC_SYS_SPSRCR_OFFSET					.equ	h'0008
CC_SYS_SPLLCR_OFFSET					.equ	h'000a
CC_SYS_SRR_OFFSET						.equ	h'000c
CC_SYS_STMCR_OFFSET						.equ	h'000e
CC_SYS_SDID_OFFSET						.equ	h'0010
CC_SYS_SDPR_OFFSET						.equ	h'0ff0

CC_SYS_REGSIZE							.equ	h'0ff2			; total size of SYSTEM regs in CC ASIC

CC_SYS_SMSCR							.equ	CC_SYS_REGBASE + CC_SYS_SMSCR_OFFSET
CC_SYS_SCONFR							.equ	CC_SYS_REGBASE + CC_SYS_SCONFR_OFFSET
CC_SYS_SBCR								.equ	CC_SYS_REGBASE + CC_SYS_SBCR_OFFSET
CC_SYS_SPCCR							.equ	CC_SYS_REGBASE + CC_SYS_SPCCR_OFFSET
CC_SYS_SPSRCR							.equ	CC_SYS_REGBASE + CC_SYS_SPSRCR_OFFSET
CC_SYS_SPLLCR							.equ	CC_SYS_REGBASE + CC_SYS_SPLLCR_OFFSET
CC_SYS_SRR								.equ	CC_SYS_REGBASE + CC_SYS_SRR_OFFSET
CC_SYS_STMCR							.equ	CC_SYS_REGBASE + CC_SYS_STMCR_OFFSET
CC_SYS_SDID								.equ	CC_SYS_REGBASE + CC_SYS_SDID_OFFSET
CC_SYS_SDPR								.equ	CC_SYS_REGBASE + CC_SYS_SDPR_OFFSET

; System Module Standby Control Register (SMSCR)

CC_SYS_SMSCR_LCDST						.equ	h'2000			; HD64463 only
CC_SYS_SMSCR_UART0ST					.equ	h'0800			; HD64463 only
CC_SYS_SMSCR_UART1ST					.equ	h'0400			; HD64463 only
CC_SYS_SMSCR_USBST						.equ	h'0080			; HD64463 only

CC_SYS_SMSCR_PS2ST						.equ	h'4000			; HD64465 only 99-08-11 cea

CC_SYS_SMSCR_ADCST						.equ	h'1000
CC_SYS_SMSCR_UARTST						.equ	h'0800
CC_SYS_SMSCR_SCDIST						.equ	h'0200
CC_SYS_SMSCR_PPST						.equ	h'0100
CC_SYS_SMSCR_PC0ST						.equ	h'0040
CC_SYS_SMSCR_PC1ST						.equ	h'0020
CC_SYS_SMSCR_AFEST						.equ	h'0010
CC_SYS_SMSCR_TM0ST						.equ	h'0008
CC_SYS_SMSCR_TM1ST						.equ	h'0004
CC_SYS_SMSCR_IRDAST						.equ	h'0002
CC_SYS_SMSCR_KBCST						.equ	h'0001

; System Configuration Register (SCONFR)

CC_SYS_SCONFR_SLS						.equ	h'2000			; HD64463 only
CC_SYS_SCONFR_LCDCD_DIVID_3				.equ	h'0080			; HD64463 only
CC_SYS_SCONFR_LCDCD_DIVID_2				.equ	h'0040			; HD64463 only
CC_SYS_SCONFR_LCDCD_DIVID_1				.equ	h'0000			; HD64463 only
CC_SYS_SCONFR_ILCDMS					.equ	h'0020			; HD64463 only

CC_SYS_SCONFR_HWEN						.equ	h'1000
CC_SYS_SCONFR_HW1						.equ	h'0100
CC_SYS_SCONFR_HW2						.equ	h'0200
CC_SYS_SCONFR_HW3						.equ	h'0300
CC_SYS_SCONFR_HW4						.equ	h'0400
CC_SYS_SCONFR_HW5						.equ	h'0500
CC_SYS_SCONFR_HW6						.equ	h'0600
CC_SYS_SCONFR_HW7						.equ	h'0700
CC_SYS_SCONFR_HW8						.equ	h'0800
CC_SYS_SCONFR_HW9						.equ	h'0900
CC_SYS_SCONFR_HW10						.equ	h'0a00
CC_SYS_SCONFR_HW11						.equ	h'0b00
CC_SYS_SCONFR_HW12						.equ	h'0c00
CC_SYS_SCONFR_HW13						.equ	h'0d00
CC_SYS_SCONFR_HW14						.equ	h'0e00
CC_SYS_SCONFR_HW15						.equ	h'0f00

CC_SYS_SCONFR_USBCKS					.equ	h'0020
CC_SYS_SCONFR_SCDICKS					.equ	h'0010

CC_SYS_SCONFR_PPFMS_ECP_EPP				.equ	h'000b
CC_SYS_SCONFR_PPFMS_ECP					.equ	h'0008
CC_SYS_SCONFR_PPFMS_EPP					.equ	h'0004
CC_SYS_SCONFR_PPFMS_SPP					.equ	h'0000

CC_SYS_SCONFR_KBWUP						.equ	h'0002

; System Bus Control Register (SBCR)

CC_SYS_SBCR_LCDIG						.equ	h'0080			; HD64463 only

CC_SYS_SBCR_PDOF						.equ	h'8000			; HD64465 only
CC_SYS_SBCR_PDIG						.equ	h'4000			; HD64465 only
CC_SYS_SBCR_PCOF						.equ	h'2000			; HD64465 only
CC_SYS_SBCR_PCIG						.equ	h'1000			; HD64465 only
CC_SYS_SBCR_PBOF						.equ	h'0800
CC_SYS_SBCR_PBIG						.equ	h'0400
CC_SYS_SBCR_PAOF						.equ	h'0200
CC_SYS_SBCR_PAIG						.equ	h'0100
CC_SYS_SBCR_CSPE						.equ	h'0040
CC_SYS_SBCR_CMDPE						.equ	h'0020
CC_SYS_SBCR_ADDRPE						.equ	h'0010
CC_SYS_SBCR_DATAPE						.equ	h'0008
CC_SYS_SBCR_CPUBIG						.equ	h'0004
CC_SYS_SBCR_PEOF						.equ	h'0002			; HD64465 only
CC_SYS_SBCR_PEIG						.equ	h'0001			; HD64465 only

; SYSTEM Peripheral Clock Control Register

CC_SYS_SPCCR_URT1CLK					.equ	h'4000			; HD64463 only
CC_SYS_SPCCR_URT0CLK					.equ	h'2000			; HD64463 only
CC_SYS_SPCCR_LCKOSC						.equ	h'0004			; HD64463 only

CC_SYS_SPCCR_ADCCLK						.equ	h'8000
CC_SYS_SPCCR_UARTCLK					.equ	h'2000
CC_SYS_SPCCR_PPCLK						.equ	h'1000
CC_SYS_SPCCR_FIRCLK						.equ	h'0800
CC_SYS_SPCCR_SIRCLK						.equ	h'0400
CC_SYS_SPCCR_SCDICLK					.equ	h'0200
CC_SYS_SPCCR_KBCCLK						.equ	h'0100
CC_SYS_SPCCR_USBCLK						.equ	h'0080
CC_SYS_SPCCR_AFECLK						.equ	h'0040
CC_SYS_SPCCR_UCKOSC						.equ	h'0002
CC_SYS_SPCCR_AFEOSC						.equ	h'0001

; System Peripheral S/W Reset Control Register (SPSRCR)

CC_SYS_SPSRCR_LCDCSRT					.equ	h'2000			; HD64463 only
CC_SYS_SPSRCR_UR0SRT					.equ	h'0800			; HD64463 only
CC_SYS_SPSRCR_UR1SRT					.equ	h'0400			; HD64463 only

CC_SYS_SPSRCR_SPORST					.equ	h'8000
CC_SYS_SPSRCR_ADCSRT					.equ	h'1000
CC_SYS_SPSRCR_UARTSRT					.equ	h'0800
CC_SYS_SPSRCR_SCDISRT					.equ	h'0200
CC_SYS_SPSRCR_PPSRT						.equ	h'0100
CC_SYS_SPSRCR_USBSRT					.equ	h'0080
CC_SYS_SPSRCR_PC0SRT					.equ	h'0040
CC_SYS_SPSRCR_PC1RST					.equ	h'0020
CC_SYS_SPSRCR_AFERST					.equ	h'0010
CC_SYS_SPSRCR_TM0RST					.equ	h'0008
CC_SYS_SPSRCR_TM1RST					.equ	h'0004
CC_SYS_SPSRCR_IRDARST					.equ	h'0002
CC_SYS_SPSRCR_KBCRST					.equ	h'0001

; System PLL Control Register (SPLLCR)

CC_SYS_SPLLCR_PLL2SB					.equ	h'0020
CC_SYS_SPLLCR_PLL1SB					.equ	h'0010
CC_SYS_SPLLCR_PLL2BP					.equ	h'0002
CC_SYS_SPLLCR_PLL1BP					.equ	h'0001

; System Test Mode Control Register (STMCR)

CC_SYS_STMCR_DITST						.equ	h'0400
CC_SYS_STMCR_DOTST						.equ	h'0200
CC_SYS_STMCR_AFETST						.equ	h'0100
CC_SYS_STMCR_PCITST						.equ	h'0080
CC_SYS_STMCR_SDBST						.equ	h'0040
CC_SYS_STMCR_USBST						.equ	h'0020
CC_SYS_STMCR_PLL2TST					.equ	h'0010
CC_SYS_STMCR_PLL1TST					.equ	h'0008
CC_SYS_STMCR_URTTST						.equ	h'0004
CC_SYS_STMCR_ACTST						.equ	h'0002
CC_SYS_STMCR_DCTST						.equ	h'0001

;
; GPIO regs
;

	.aif ENABLE_HD64464 eq h'00
CC_GPIO_REGBASE_463						.equ	HD64463_BASE + HD64463_GPIO_OFFSET
	.aendi
CC_GPIO_REGBASE							.equ	HD64465_BASE + HD64465_GPIO_OFFSET

CC_GPIO_GPACR_OFFSET					.equ	h'0000	; Port A Control Reg Offset Address 
CC_GPIO_GPBCR_OFFSET					.equ	h'0002	; Port B Control Reg Offset Address 
CC_GPIO_GPCCR_OFFSET					.equ	h'0004	; Port C Control Reg Offset Address 
CC_GPIO_GPDCR_OFFSET					.equ	h'0006	; Port D Control Reg Offset Address 
CC_GPIO_GPECR_OFFSET					.equ	h'0008	; Port E Control Reg Offset Address 

CC_GPIO_GPADR_OFFSET					.equ	h'0010	; Port A Data Reg Offset Address 
CC_GPIO_GPBDR_OFFSET					.equ	h'0012	; Port B Data Reg Offset Address 
CC_GPIO_GPCDR_OFFSET					.equ	h'0014	; Port C Data Reg Offset Address 
CC_GPIO_GPDDR_OFFSET					.equ	h'0016	; Port D Data Reg Offset Address 
CC_GPIO_GPEDR_OFFSET					.equ	h'0018	; Port E Data Reg Offset Address 

CC_GPIO_GPAICR_OFFSET					.equ	h'0020	; Port A Interrupt Control Reg Offset Address 
CC_GPIO_GPBICR_OFFSET					.equ	h'0022	; Port B Interrupt Control Reg Offset Address 
CC_GPIO_GPCICR_OFFSET					.equ	h'0024	; Port C Interrupt Control Reg Offset Address 
CC_GPIO_GPDICR_OFFSET					.equ	h'0026	; Port D Interrupt Control Reg Offset Address 
CC_GPIO_GPEICR_OFFSET					.equ	h'0028	; Port E Interrupt Control Reg Offset Address 
	
CC_GPIO_GPAISR_OFFSET					.equ	h'0040	; Port A Interrupt Status Reg Offset Address 
CC_GPIO_GPBISR_OFFSET					.equ	h'0042	; Port B Interrupt Status Reg Offset Address 
CC_GPIO_GPCISR_OFFSET					.equ	h'0044	; Port C Interrupt Status Reg Offset Address 
CC_GPIO_GPDISR_OFFSET					.equ	h'0046	; Port D Interrupt Status Reg Offset Address 
CC_GPIO_GPEISR_OFFSET					.equ	h'0048	; Port E Interrupt Status Reg Offset Address 

CC_GPIO_REGSIZE							.equ	h'0050

CC_GPIO_GPACR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPACR_OFFSET	; Port A Control Reg 
CC_GPIO_GPBCR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPBCR_OFFSET	; Port B Control Reg 
CC_GPIO_GPCCR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPCCR_OFFSET	; Port C Control Reg 
CC_GPIO_GPDCR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPDCR_OFFSET	; Port D Control Reg 
CC_GPIO_GPECR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPECR_OFFSET	; Port E Control Reg 

CC_GPIO_GPADR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPADR_OFFSET	; Port A Data Reg 
CC_GPIO_GPBDR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPBDR_OFFSET	; Port B Data Reg 
CC_GPIO_GPCDR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPCDR_OFFSET	; Port C Data Reg 
CC_GPIO_GPDDR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPDDR_OFFSET	; Port D Data Reg 
CC_GPIO_GPEDR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPEDR_OFFSET	; Port E Data Reg 

CC_GPIO_GPAICR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPAICR_OFFSET	; Port A Interrupt Control Reg 
CC_GPIO_GPBICR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPBICR_OFFSET	; Port B Interrupt Control Reg 
CC_GPIO_GPCICR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPCICR_OFFSET	; Port C Interrupt Control Reg 
CC_GPIO_GPDICR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPDICR_OFFSET	; Port D Interrupt Control Reg 
CC_GPIO_GPEICR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPEICR_OFFSET	; Port E Interrupt Control Reg 
	
CC_GPIO_GPAISR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPAISR_OFFSET	; Port A Interrupt Status Reg 
CC_GPIO_GPBISR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPBISR_OFFSET	; Port B Interrupt Status Reg 
CC_GPIO_GPCISR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPCISR_OFFSET	; Port C Interrupt Status Reg 
CC_GPIO_GPDISR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPDISR_OFFSET	; Port D Interrupt Status Reg 
CC_GPIO_GPEISR							.equ	CC_GPIO_REGBASE + CC_GPIO_GPEISR_OFFSET	; Port E Interrupt Status Reg 

;
; The companion chip interrupt controller
;

	.aif ENABLE_HD64464 eq h'00
CC_INTC_REGBASE_463						.equ	HD64463_BASE + HD64463_INTC_OFFSET
	.aendi
CC_INTC_REGBASE							.equ	HD64465_BASE + HD64465_INTC_OFFSET
CC_INTC_NIRR_OFFSET						.equ	h'0000									; Interrupt Request Register Address Offset
CC_INTC_NIMR_OFFSET						.equ	h'0002									; Interrupt Mask Register Address Offset

CC_INTC_NIRR							.equ	CC_INTC_REGBASE + CC_INTC_NIRR_OFFSET	; Interrupt Request Register Address Offset
CC_INTC_NIMR							.equ	CC_INTC_REGBASE + CC_INTC_NIMR_OFFSET

; Interrupt Request Register (NIRR)

CC_INTC_NIRR_PS2KBR		.equ	0x8000		; PS/2 Keyboard interrupt HD64465 only 99-08-11 cea
CC_INTC_NIRR_PS2MSR		.equ	0x0080		; PS/2 mouse interrupt    HD64465 only 99-08-11 cea

CC_INTC_NIRR_PCC0R						.equ	h'4000	;	PCC0R	interrupt	
CC_INTC_NIRR_PCC1R						.equ	h'2000	;	PCC1R	interrupt	
CC_INTC_NIRR_AFER						.equ	h'1000	;	AFER	interrupt	
CC_INTC_NIRR_GPIOR						.equ	h'0800	;	GPIOR	interrupt	
CC_INTC_NIRR_TMU0R						.equ	h'0400	;	TMU0R	interrupt	
CC_INTC_NIRR_TMU1R						.equ	h'0200	;	TMU1R	interrupt	
CC_INTC_NIRR_KBCR						.equ	h'0100	;	KBDR	interrupt	
CC_INTC_NIRR_IRDAR						.equ	h'0040	;	IRDAR	interrupt	
CC_INTC_NIRR_UART0R						.equ	h'0020	;	UART0R	interrupt	
CC_INTC_NIRR_UART1R						.equ	h'0010	;	UART1R	interrupt	
CC_INTC_NIRR_PPR						.equ	h'0008	;	PPR		interrupt	
CC_INTC_NIRR_SCDIR						.equ	h'0004	;	SCDIR	interrupt	
CC_INTC_NIRR_USBR						.equ	h'0002	;	USBR	interrupt	
CC_INTC_NIRR_ADCR						.equ	h'0001	;	ADCR	interrupt	

; Interrupt Mask Register (NIMR)

CC_INTC_NIMR_ALL_MASK					.equ	h'ffff	;	all	interrupt	mask

CC_INTC_NIMR_PS2KBM_MASK	.equ	0x8000		; PS/2 Keyboard mask HD64465 only 99-08-11 cea
CC_INTC_NIMR_PS2MSM_MASK	.equ	0x0080		; PS/2 mouse mask    HD64465 only 99-08-11 cea

CC_INTC_NIMR_PCC0M_MASK					.equ	h'4000	;	PCC0M	interrupt	mask
CC_INTC_NIMR_PCC1M_MASK					.equ	h'2000	;	PCC1M	interrupt	mask
CC_INTC_NIMR_AFEM_MASK					.equ	h'1000	;	AFEM	interrupt	mask
CC_INTC_NIMR_GPIOM_MASK					.equ	h'0800	;	GPIOM	interrupt	mask