cc.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#define CC_CODEC_ATSR_PLFETFOV						0x00002000
#define CC_CODEC_ATSR_L2TFOV						0x00001000
#define CC_CODEC_ATSR_HTTFOV						0x00000800
#define CC_CODEC_ATSR_IOCTFOV						0x00000400

#define CC_CODEC_ATSR_PLTFUN						0x00000200
#define CC_CODEC_ATSR_PRTFUN						0x00000100
#define CC_CODEC_ATSR_L1TFUN						0x00000080
#define CC_CODEC_ATSR_PCTFUN						0x00000040
#define CC_CODEC_ATSR_PLSTFUN						0x00000020
#define CC_CODEC_ATSR_PRSTFUN						0x00000010
#define CC_CODEC_ATSR_PLFETFUN						0x00000008
#define CC_CODEC_ATSR_L2TFUN						0x00000004
#define CC_CODEC_ATSR_HTTFUN						0x00000002
#define CC_CODEC_ATSR_IOCTFUN						0x00000001

// AC97 RX FIFO Interrupt Enable Register (ARIER)

#define CC_CODEC_ARIER_STARYIE						0x00400000
#define CC_CODEC_ARIER_STDRYIE						0x00200000

#define CC_CODEC_ARIER_PLRFRQIE						0x00100000
#define CC_CODEC_ARIER_PRRFRQIE						0x00080000
#define CC_CODEC_ARIER_L1RFRQIE						0x00040000
#define CC_CODEC_ARIER_MICRFRQIE					0x00020000
#define CC_CODEC_ARIER_L2RFRQIE						0x00010000
#define CC_CODEC_ARIER_HTRFRQIE						0x00008000
#define CC_CODEC_ARIER_IOCSRFRQIE					0x00004000

#define CC_CODEC_ARIER_PLRFOVIE						0x00002000
#define CC_CODEC_ARIER_PRRFOVIE						0x00001000
#define CC_CODEC_ARIER_L1RFOVIE						0x00000800
#define CC_CODEC_ARIER_MICRFOVIE					0x00000400
#define CC_CODEC_ARIER_L2RFOVIE						0x00000200
#define CC_CODEC_ARIER_HTRFOVIE						0x00000100
#define CC_CODEC_ARIER_IOCSRFOVIE					0x00000080

#define CC_CODEC_ARIER_PLRFUNIE						0x00000040
#define CC_CODEC_ARIER_PRRFUNIE						0x00000020
#define CC_CODEC_ARIER_L1RFUNIE						0x00000010
#define CC_CODEC_ARIER_MICRFUNIE					0x00000008
#define CC_CODEC_ARIER_L2RFUNIE						0x00000004
#define CC_CODEC_ARIER_HTRFUNIE						0x00000002
#define CC_CODEC_ARIER_IOCSRFUNIE					0x00000001

// AC97 RX FIFO Status Register (ARSR)

#define CC_CODEC_ARSR_STARY							0x00400000
#define CC_CODEC_ARSR_STDRY							0x00200000

#define CC_CODEC_ARSR_PLRFRQ						0x00100000
#define CC_CODEC_ARSR_PRRFRQ						0x00080000
#define CC_CODEC_ARSR_L1RFRQ						0x00040000
#define CC_CODEC_ARSR_MICRFRQ						0x00020000
#define CC_CODEC_ARSR_L2RFRQ						0x00010000
#define CC_CODEC_ARSR_HTRFRQ						0x00008000
#define CC_CODEC_ARSR_IOCSRFRQ						0x00004000

#define CC_CODEC_ARSR_PLRFOV						0x00002000
#define CC_CODEC_ARSR_PRRFOV						0x00001000
#define CC_CODEC_ARSR_L1RFOV						0x00000800
#define CC_CODEC_ARSR_MICRFOV						0x00000400
#define CC_CODEC_ARSR_L2RFOV						0x00000200
#define CC_CODEC_ARSR_HTRFOV						0x00000100
#define CC_CODEC_ARSR_IOCSRFOV						0x00000080

#define CC_CODEC_ARSR_PLRFUN						0x00000040
#define CC_CODEC_ARSR_PRRFUN						0x00000020
#define CC_CODEC_ARSR_L1RFUN						0x00000010
#define CC_CODEC_ARSR_MICRFUN						0x00000008
#define CC_CODEC_ARSR_L2RFUN						0x00000004
#define CC_CODEC_ARSR_HTRFUN						0x00000002
#define CC_CODEC_ARSR_IOCSRFUN						0x00000001

// AC97 Control Register (ACR)

#define CC_CODEC_ACR_VS								0x80000000
#define CC_CODEC_ACR_RXDMA_EN						0x00400000
#define CC_CODEC_ACR_TXDMA_EN						0x00200000
#define CC_CODEC_ACR_FCAF							0x00100000
#define CC_CODEC_ACR_FCDF							0x00080000
#define CC_CODEC_ACR_FSTAF							0x00040000
#define CC_CODEC_ACR_FSTDF							0x00020000
#define CC_CODEC_ACR_FPLTF							0x00010000
#define CC_CODEC_ACR_FPRTF							0x00008000
#define CC_CODEC_ACR_FL1TF							0x00004000
#define CC_CODEC_ACR_FPCTF							0x00002000
#define CC_CODEC_ACR_FPLSTF							0x00001000
#define CC_CODEC_ACR_FPRSTF							0x00000800
#define CC_CODEC_ACR_FPLETF							0x00000400
#define CC_CODEC_ACR_FL2TF							0x00000200
#define CC_CODEC_ACR_FHTF							0x00000100
#define CC_CODEC_ACR_FIOCTF							0x00000080
#define CC_CODEC_ACR_FPLRF							0x00000040
#define CC_CODEC_ACR_FPRRF							0x00000020
#define CC_CODEC_ACR_FL1RF							0x00000010
#define CC_CODEC_ACR_FMRF							0x00000008
#define CC_CODEC_ACR_FL2RF							0x00000004
#define CC_CODEC_ACR_FHRF							0x00000002
#define CC_CODEC_ACR_FIOSRF							0x00000001

//AC97 TAG Register (ATAGR)

#define CC_CODEC_ATAGR_CR							0x80000000

//Slot Request Active Register (SRAR)

#define CC_CODEC_SRAR_SL12RA						0x1000
#define CC_CODEC_SRAR_SL11RA						0x0800
#define CC_CODEC_SRAR_SL10RA						0x0400
#define CC_CODEC_SRAR_SL9RA							0x0200
#define CC_CODEC_SRAR_SL8RA							0x0100
#define CC_CODEC_SRAR_SL7RA							0x0080
#define CC_CODEC_SRAR_SL6RA							0x0040
#define CC_CODEC_SRAR_SL5RA							0x0020
#define CC_CODEC_SRAR_SL4RA							0x0010
#define CC_CODEC_SRAR_SL3RA							0x0008

//
// definitions for the Audio Front End on the companion chip (all the registers are 16 bits wide)
//
#if ENABLE_HD64464!=1
#define CC_AFE_REGBASE_463							(HD64463_BASE + HD64463_AFE_OFFSET)
#endif
#define CC_AFE_REGBASE								(HD64465_BASE + HD64465_AFE_OFFSET)

#define CC_AFE_RXDB0_OFFSET							0x0000		// Receive buffer 0 
#define CC_AFE_RXDB1_OFFSET							0x0000		// Receive buffer 1 (same offset!) 
#define CC_AFE_TXDB0_OFFSET							0x0100		// Transmit buffer 0 
#define CC_AFE_TXDB1_OFFSET							0x0100		// Transmit buffer 1 (same offset!) 
#define CC_AFE_CTR_OFFSET							0x0200		// Control register 
#define CC_AFE_STR_OFFSET							0x0202		// Status register 
#define CC_AFE_RXDR_OFFSET							0x0204		// Receive data register 
#define CC_AFE_TXDR_OFFSET							0x0206		// Transmit data register 

#define CC_AFE_REGSIZE								0x0208		// total size of AFE registers 

#define CC_AFE_RXDB0								(CC_AFE_REGBASE + CC_AFE_RXDB0_OFFSET)	// Receive buffer 0 
#define CC_AFE_RXDB1								(CC_AFE_REGBASE + CC_AFE_RXDB1_OFFSET)	// Receive buffer 1 (same offset!) 
#define CC_AFE_TXDB0								(CC_AFE_REGBASE + CC_AFE_TXDB0_OFFSET)	// Transmit buffer 0 
#define CC_AFE_TXDB1								(CC_AFE_REGBASE + CC_AFE_TXDB1_OFFSET)	// Transmit buffer 1 (same offset!) 
#define CC_AFE_CTR									(CC_AFE_REGBASE + CC_AFE_CTR_OFFSET)		// Control register 
#define CC_AFE_STR									(CC_AFE_REGBASE + CC_AFE_STR_OFFSET)		// Status register 
#define CC_AFE_RXDR									(CC_AFE_REGBASE + CC_AFE_RXDR_OFFSET)		// Receive data register 
#define CC_AFE_TXDR									(CC_AFE_REGBASE + CC_AFE_TXDR_OFFSET)		// Transmit data register 

//
// definitions of DISPLAY interface (DSP) HD64463 BASE
//
#if (ENABLE_HD64464!=1 && (ENABLE_MQ200 !=1))
#define CC_DSP_REGBASE								(HD64463_BASE + HD64463_LCDC_OFFSET)
#define CC_DSP_LCDCBAR_OFFSET						0x0000		// Base Address Register Offset Address 
#define CC_DSP_LCDCLOR_OFFSET						0x0002		// Line address offset register  Offset Address
#define	CC_DSP_LCDCCR_OFFSET						0x0004		// Control Register  Offset Address
#define CC_DSP_LDR1_OFFSET							0x0010		// LCD Display regsiter 1  Offset Address
#define CC_DSP_LDR2_OFFSET							0x0012		// LCD Display register 2  Offset Address
#define CC_DSP_LDHNCR_OFFSET						0x0014		// Num Chars in Horz. reg  Offset Address
#define CC_DSP_LDHNSR_OFFSET						0x0016		// Start Position of Horz. reg  Offset Address
#define CC_DSP_LDVNTR_OFFSET						0x0018		// Total Vertical Lines reg  Offset Address
#define CC_DSP_LDVNDR_OFFSET						0x001A		// Display Vertical Lines reg  Offset Address
#define CC_DSP_LDVSPR_OFFSET						0x001C		// Vertical Synchronous Pos. Reg  Offset Address
#define CC_DSP_LDR3_OFFSET							0x001E		// LCD Display register 3  Offset Address
#define CC_DSP_CRTVTR_OFFSET						0x0020		// CRT Vertical Total Register  Offset Address
#define CC_DSP_CRTVRSR_OFFSET						0x0022		// CRT Vertical Retrace Start Register  Offset Address
#define CC_DSP_CRTVRER_OFFSET						0x0024		// CRT Vertical Retrace End Register  Offset Address
#define CC_DSP_CPTWAR_OFFSET						0x0030		// Color Palette Write Addr Reg  Offset Address
#define CC_DSP_CPTWDR_OFFSET						0x0032		// Color Palette Write Data Reg  Offset Address
#define CC_DSP_CPTRAR_OFFSET						0x0034		// Color Palette Read Address Reg  Offset Address
#define CC_DSP_CPTRDR_OFFSET						0x0036		// Color Palette Read data reg  Offset Address

#define CC_DSP_REGSIZE								0x0038		// total size of DSP ASIC regs 

#define CC_DSP_LCDCBAR								(CC_DSP_REGBASE + CC_DSP_LCDCBAR_OFFSET)	// Base Address Register 
#define CC_DSP_LCDCLOR								(CC_DSP_REGBASE + CC_DSP_LCDCLOR_OFFSET)	// Line address offset register 
#define	CC_DSP_LCDCCR								(CC_DSP_REGBASE + CC_DSP_LCDCCR_OFFSET)	// Control Register 
#define CC_DSP_LDR1									(CC_DSP_REGBASE + CC_DSP_LDR1_OFFSET)		// LCD Display regsiter 1 
#define CC_DSP_LDR2									(CC_DSP_REGBASE + CC_DSP_LDR2_OFFSET)		// LCD Display register 2 
#define CC_DSP_LDHNCR								(CC_DSP_REGBASE + CC_DSP_LDHNCR_OFFSET)	// Num Chars in Horz. reg 
#define CC_DSP_LDHNSR								(CC_DSP_REGBASE + CC_DSP_LDHNSR_OFFSET)	// Start Position of Horz. reg 
#define CC_DSP_LDVNTR								(CC_DSP_REGBASE + CC_DSP_LDVNTR_OFFSET)	// Total Vertical Lines reg 
#define CC_DSP_LDVNDR								(CC_DSP_REGBASE + CC_DSP_LDVNDR_OFFSET)	// Display Vertical Lines reg 
#define CC_DSP_LDVSPR								(CC_DSP_REGBASE + CC_DSP_LDVSPR_OFFSET)	// Vertical Synchronous Pos. Reg 
#define CC_DSP_LDR3									(CC_DSP_REGBASE + CC_DSP_LDR3_OFFSET)		// LCD Display register 3 
#define CC_DSP_CRTVTR								(CC_DSP_REGBASE + CC_DSP_CRTVTR_OFFSET)	// CRT Vertical Total Register 
#define CC_DSP_CRTVRSR								(CC_DSP_REGBASE + CC_DSP_CRTVRSR_OFFSET)	// CRT Vertical Retrace Start Register 
#define CC_DSP_CRTVRER								(CC_DSP_REGBASE + CC_DSP_CRTVRER_OFFSET)	// CRT Vertical Retrace End Register 
#define CC_DSP_CPTWAR								(CC_DSP_REGBASE + CC_DSP_CPTWAR_OFFSET)	// Color Palette Write Addr Reg 
#define CC_DSP_CPTWDR								(CC_DSP_REGBASE + CC_DSP_CPTWDR_OFFSET)	// Color Palette Write Data Reg 
#define CC_DSP_CPTRAR								(CC_DSP_REGBASE + CC_DSP_CPTRAR_OFFSET)	// Color Palette Read Address Reg 
#define CC_DSP_CPTRDR								(CC_DSP_REGBASE + CC_DSP_CPTRDR_OFFSET)	// Color Palette Read data reg 
#endif

// Companion Chip (HD64464) module offsets
#if ENABLE_HD64464==1
#define HD64464_OFFSET								0x03E00000
#define CC_DSP_REGBASE								(HD64464_BASE + HD64464_OFFSET)

#define	CC_DSP_PM_OFFSET							0x00000000
#define	CC_DSP_CC_OFFSET							0x00002000
#define	CC_DSP_MM_OFFSET							0x00004000
#define	CC_DSP_IN_OFFSET							0x00014000
#define	CC_DSP_GC_OFFSET							0x0001E000
#define	CC_DSP_GE_OFFSET							0x00020000
#define	CC_DSP_FP_OFFSET							0x00022000
#define	CC_DSP_CP1_OFFSET							0x00024000
#define	CC_DSP_CP2_OFFSET							0x00026000
#define	CC_DSP_CR_OFFSET							0x0002A000
#define CC_DSP_REGSIZE								0x00030000

#define	CC_DSP_PM									(CC_DSP_REGBASE + CC_DSP_PM_OFFSET)	// Power Management + Clock Generation
#define	CC_DSP_CC									(CC_DSP_REGBASE + CC_DSP_CC_OFFSET)	// CPU Interface
#define	CC_DSP_MM									(CC_DSP_REGBASE + CC_DSP_MM_OFFSET)	// Memory Interface
#define	CC_DSP_IN									(CC_DSP_REGBASE + CC_DSP_IN_OFFSET)	// Interrupt Controller
#define	CC_DSP_GC									(CC_DSP_REGBASE + CC_DSP_GC_OFFSET)	// Graphics Controller 1 and 2
#define	CC_DSP_GE									(CC_DSP_REGBASE + CC_DSP_GE_OFFSET)	// Graphics Engine
#define	CC_DSP_FP									(CC_DSP_REGBASE + CC_DSP_FP_OFFSET)	// Flat Panel Controller
#define	CC_DSP_CP1									(CC_DSP_REGBASE + CC_DSP_CP1_OFFSET)// Color Palette 1
#define	CC_DSP_CP2									(CC_DSP_REGBASE + CC_DSP_CP2_OFFSET)// Color Palette 2
#define	CC_DSP_CR									(CC_DSP_REGBASE + CC_DSP_CR_OFFSET)	// Configuration Registers

#endif

// Companion Chip (MQ200) module offsets
#if ENABLE_MQ200==1
#define MQ200_OFFSET								0x01E00000
#define CC_DSP_REGBASE								(MQ200_BASE + MQ200_OFFSET)

#define	CC_DSP_PM_OFFSET							0x00000000
#define	CC_DSP_CC_OFFSET							0x00002000
#define	CC_DSP_MM_OFFSET							0x00004000
#define	CC_DSP_IN_OFFSET							0x00008000
#define	CC_DSP_GC_OFFSET							0x0000A000
#define	CC_DSP_GE_OFFSET							0x0000C000
#define	CC_DSP_FP_OFFSET							0x0000E000
#define	CC_DSP_CP1_OFFSET							0x00010400//We have to chwck color palette address!
#define	CC_DSP_DC_OFFSET							0x00014000
#define	CC_DSP_PCI_OFFSET							0x00016000
#define	CC_DSP_PSF_OFFSET							0x00018000
#define CC_DSP_REGSIZE								0x0001A000

#define	CC_DSP_PM									(CC_DSP_REGBASE + CC_DSP_PM_OFFSET)	// Power Management + Clock Generation
#define	CC_DSP_CC									(CC_DSP_REGBASE + CC_DSP_CC_OFFSET)	// CPU Interface
#define	CC_DSP_MM									(CC_DSP_REGBASE + CC_DSP_MM_OFFSET)	// Memory Interface
#define	CC_DSP_IN									(CC_DSP_REGBASE + CC_DSP_IN_OFFSET)	// Interrupt Controller
#define	CC_DSP_GC									(CC_DSP_REGBASE + CC_DSP_GC_OFFSET)	// Graphics Controller 1 and 2
#define	CC_DSP_GE									(CC_DSP_REGBASE + CC_DSP_GE_OFFSET)	// Graphics Engine
#define	CC_DSP_FP									(CC_DSP_REGBASE + CC_DSP_FP_OFFSET)	// Flat Panel Controller
#define	CC_DSP_CP1									(CC_DSP_REGBASE + CC_DSP_CP1_OFFSET)// Color Palette 1
#define	CC_DSP_DC									(CC_DSP_REGBASE + CC_DSP_DC_OFFSET)	// Configuration Registers
#define	CC_DSP_PCI									(CC_DSP_REGBASE + CC_DSP_PCI_OFFSET)// PCI Configuration Registers
#define	CC_DSP_PSF									(CC_DSP_REGBASE + CC_DSP_PSF_OFFSET)// PCI Configuration Registers

#endif	//ENABLE_MQ200

#if ENABLE_HD64464!=1
#define CC_KBC_REGBASE_463							(HD64463_BASE + HD64463_KBC_OFFSET)
#endif

#define CC_KBC_REGBASE								(HD64465_BASE + HD64465_KBC_OFFSET)

#define CC_KBC_CR_OFFSET			0x800
#define CC_KBC_SR_OFFSET			0x802

#define CC_KBC_CR					(CC_KBC_REGBASE + CC_KBC_CR_OFFSET)
#define CC_KBC_SR					(CC_KBC_REGBASE + CC_KBC_SR_OFFSET)

#endif