📄 cc.h
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#define CC_UART_UIER (CC_UART_REGBASE + CC_UART_UIER_OFFSET)
#define CC_UART_UIIR (CC_UART_REGBASE + CC_UART_UIIR_OFFSET)
#define CC_UART_UFCR (CC_UART_REGBASE + CC_UART_UFCR_OFFSET)
#define CC_UART_ULCR (CC_UART_REGBASE + CC_UART_ULCR_OFFSET)
#define CC_UART_UMCR (CC_UART_REGBASE + CC_UART_UMCR_OFFSET)
#define CC_UART_UDLL (CC_UART_REGBASE + CC_UART_UDLL_OFFSET)
#define CC_UART_UDLM (CC_UART_REGBASE + CC_UART_UDLM_OFFSET)
#define CC_UART_ULSR (CC_UART_REGBASE + CC_UART_ULSR_OFFSET)
#define CC_UART_UMSR (CC_UART_REGBASE + CC_UART_UMSR_OFFSET)
#define CC_UART_USCR (CC_UART_REGBASE + CC_UART_USCR_OFFSET)
//
// Parallel Interface defines, HD64465 only 99-08-11 cea
//
#define CC_PAR_BASE_REG (HD64465_BASE + HD64465_PARALLEL_OFFSET)
#define CC_PAR_DATA_REG CC_PAR_BASE_REG + 0x00
#define CC_PAR_STATUS_REG CC_PAR_BASE_REG + 0x02
#define CC_PAR_CONTROL_REG CC_PAR_BASE_REG + 0x04
#define CC_PAR_ECP_DATA_REG CC_PAR_BASE_REG + 0x10
#define CC_PAR_EXT_CONTROL_REG CC_PAR_BASE_REG + 0x14
/* CC_PAR_EXT_CONTROL_REG mode bits
Bits 7-5 select mode,
000 = SPP
001 = PS/2 Parallel mode
010 = Parallel Port FIFO mode
011 = ECP Parallel Port mode
100 = Reserved
101 = Reserved
110 = Test mode
111 = Configuration mode
Bit 4 Error Interrupt Enable (nErrIntrEn) 0=enable, 1=disable
Bit 2 Service Interrupt (ServiceIntr) 0=enable, 1=disable
*/
#define CC_PAR_SPP_MODE (0x14)
#define CC_PAR_PS2_MODE (0x34)
#define CC_PAR_ECP_MODE (0x74)
#define CC_PAR_TEST_MODE (0xC0)
/* The WinCE documentation for the D9000
parallel port uses some variation in
the names of the parallel port bits.
The D9000 uses a 36 pin Centronics connector
on the debug interface board. This interface
seems to designed to look like a printer.
The S1 uses a 25 pin D-type connector. this
interface is designed to look like a host. To
make the S1 to behave like a printer is tricky.
DB25 (S1) Cen-36 (D9000)
DIR Pin# DIR Pin#
O 1 CC_PAR_STROBE I 1 DF_PAR_STROBE
I/O 2-9 (data bus) I/O 2-9 (data bus)
I 10 CC_PAR_NACK O 10 DF_PAR_NACK
I 11 CC_PAR_BUSY O 11 DF_PAR_BUSY
I 12 CC_PAR_PE O 12 DF_PAR_ERROR
I 13 CC_PAR_SELECT O 13 DF_PAR_SELECT
O 14 CC_PAR_AUTOFD I 14 DF_PAR_AUTOFD
I 15 CC_PAR_ERROR O 32 DF_PAR_NFAULT
O 16 CC_PAR_INIT I 31 DF_PAR_INIT
O 17 CC_PAR_SELECTIN I 36 DF_PAR_SELECTIN
CC_PAR_READDIR DF_PAR_EN
CC_PAR_IRQEN DF_PAR_INTR_MASK
--------------------------------------------------
The WinCE help data base describes a cable
to connect the development workstation to
a WinCE target. This is the cable used to
connect to the HD64465 parallel port.
*/
// CC_PAR_STATUS_REG bits
#define CC_PAR_BUSY 0x80
#define CC_PAR_NACK 0x40
#define CC_PAR_PE 0x20
#define CC_PAR_SELECT 0x10
#define CC_PAR_ERROR 0x08
// CC_PAR_CONTROL_REG bits
// CC_PAR_READDIR,0 = output, 1 = input
#define CC_PAR_READDIR 0x20
#define CC_PAR_IRQEN 0x10
#define CC_PAR_SELECTIN 0x08
#define CC_PAR_INIT 0x04
#define CC_PAR_AUTOFD 0x02
#define CC_PAR_STROBE 0x01
// CC_PAR_EXT_CONTROL_REG bits
#define CC_PAR_NERRINTRE 0x10
#define CC_PAR_SERVICEINTR 0x04
#define CC_PAR_OUT_FULL 0x02
#define CC_PAR_IN_EMPTY 0x01
//
// Serial CODEC Interface defines
//
#if ENABLE_HD64464!=1
#define CC_CODEC_REGBASE_463 (HD64463_BASE + HD64463_CODEC_OFFSET)
#endif
#define CC_CODEC_REGBASE (HD64465_BASE + HD64465_CODEC_OFFSET)
#define CC_CODEC_REGSIZE 0x0070
#define CC_CODEC_TDR_OFFSET 0x0000
#define CC_CODEC_RDR_OFFSET 0x0004
#define CC_CODEC_CR_OFFSET 0x0008
#define CC_CODEC_SR_OFFSET 0x000C
#define CC_CODEC_FSR_OFFSET 0x0010
#define CC_CODEC_CAR_OFFSET 0x0020
#define CC_CODEC_CDR_OFFSET 0x0024
#define CC_CODEC_PCML_OFFSET 0x0028
#define CC_CODEC_PCMR_OFFSET 0x002C
#define CC_CODEC_LINE1_OFFSET 0x0030
#define CC_CODEC_PCMC_OFFSET 0x0034
#define CC_CODEC_PCMLS_OFFSET 0x0038
#define CC_CODEC_PCMRS_OFFSET 0x003C
#define CC_CODEC_PCMLFE_OFFSET 0x0040
#define CC_CODEC_LINE2_OFFSET 0x0044
#define CC_CODEC_HSET_OFFSET 0x0048
#define CC_CODEC_IOCS_OFFSET 0x004C
#define CC_CODEC_ATIER_OFFSET 0x0050
#define CC_CODEC_ATSR_OFFSET 0x0054
#define CC_CODEC_ARIER_OFFSET 0x0058
#define CC_CODEC_ARSR_OFFSET 0x005C
#define CC_CODEC_ACR_OFFSET 0x0060
#define CC_CODEC_ATAGR_OFFSET 0x0064
#define CC_CODEC_SRAR_OFFSET 0x0068
#define CC_CODEC_TDR (CC_CODEC_REGBASE + CC_CODEC_TDR_OFFSET)
#define CC_CODEC_RDR (CC_CODEC_REGBASE + CC_CODEC_RDR_OFFSET)
#define CC_CODEC_CR (CC_CODEC_REGBASE + CC_CODEC_CR_OFFSET)
#define CC_CODEC_SR (CC_CODEC_REGBASE + CC_CODEC_SR_OFFSET)
#define CC_CODEC_FSR (CC_CODEC_REGBASE + CC_CODEC_FSR_OFFSET)
#define CC_CODEC_CAR (CC_CODEC_REGBASE + CC_CODEC_CAR_OFFSET)
#define CC_CODEC_CDR (CC_CODEC_REGBASE + CC_CODEC_CDR_OFFSET)
#define CC_CODEC_PCML (CC_CODEC_REGBASE + CC_CODEC_PCML_OFFSET)
#define CC_CODEC_PCMR (CC_CODEC_REGBASE + CC_CODEC_PCMR_OFFSET)
#define CC_CODEC_LINE1 (CC_CODEC_REGBASE + CC_CODEC_LINE1_OFFSET)
#define CC_CODEC_PCMC (CC_CODEC_REGBASE + CC_CODEC_PCMC_OFFSET)
#define CC_CODEC_PCMLS (CC_CODEC_REGBASE + CC_CODEC_PCMLS_OFFSET)
#define CC_CODEC_PCMRS (CC_CODEC_REGBASE + CC_CODEC_PCMRS_OFFSET)
#define CC_CODEC_PCMLFE (CC_CODEC_REGBASE + CC_CODEC_PCMLFE_OFFSET)
#define CC_CODEC_LINE2 (CC_CODEC_REGBASE + CC_CODEC_LINE2_OFFSET)
#define CC_CODEC_HSET (CC_CODEC_REGBASE + CC_CODEC_HSET_OFFSET)
#define CC_CODEC_IOCS (CC_CODEC_REGBASE + CC_CODEC_IOCS_OFFSET)
#define CC_CODEC_ATIER (CC_CODEC_REGBASE + CC_CODEC_ATIER_OFFSET)
#define CC_CODEC_ATSR (CC_CODEC_REGBASE + CC_CODEC_ATSR_OFFSET)
#define CC_CODEC_ARIER (CC_CODEC_REGBASE + CC_CODEC_ARIER_OFFSET)
#define CC_CODEC_ARSR (CC_CODEC_REGBASE + CC_CODEC_ARSR_OFFSET)
#define CC_CODEC_ACR (CC_CODEC_REGBASE + CC_CODEC_ACR_OFFSET)
#define CC_CODEC_ATAGR (CC_CODEC_REGBASE + CC_CODEC_ATAGR_OFFSET)
#define CC_CODEC_SRAR (CC_CODEC_REGBASE + CC_CODEC_SRAR_OFFSET)
// Control Register (CR)
#define CC_CODEC_CR_DMAEN 0x2000
#define CC_CODEC_CR_SL18 0x1000
#define CC_CODEC_CR_CDRT 0x0800
#define CC_CODEC_CR_WMRT 0x0400
#define CC_CODEC_CR_AC97S 0x0200
#define CC_CODEC_CR_SWR 0x0100
#define CC_CODEC_CR_PU 0x0080
#define CC_CODEC_CR_MS 0x0040
#define CC_CODEC_CR_ST 0x0020
#define CC_CODEC_CR_CRE 0x0010
#define CC_CODEC_CR_FTF 0x0008
#define CC_CODEC_CR_TXEN 0x0004
#define CC_CODEC_CR_FRF 0x0002
#define CC_CODEC_CR_RXEN 0x0001
// Status Register (SR)
#define CC_CODEC_SR_IR71 0x4000
#define CC_CODEC_SR_TNF 0x2000
#define CC_CODEC_SR_TFS_E1E0 0x0000 // (FIFO-1, FIFO-0):(EMPTY, EMPTY)
#define CC_CODEC_SR_TFS_E1N0 0x0800 // (FIFO-1, FIFO-0):(EMPTY, NOT EMPTY)
#define CC_CODEC_SR_TFS_N1E0 0x1000 // (FIFO-1, FIFO-0):(NOT EMPTY, EMPTY)
#define CC_CODEC_SR_TFS_N1N0 0x1800 // (FIFO-1, FIFO-0):(NOT EMPTY, NOT EMPTY)
#define CC_CODEC_SR_TFU 0x0400
#define CC_CODEC_SR_TFO 0x0200
#define CC_CODEC_SR_TDI 0x0100
#define CC_CODEC_SR_RNE 0x0020
#define CC_CODEC_SR_RFS_N1N0 0x0000 // (FIFO-1, FIFO-0):(NOT FULL, NOT FULL)
#define CC_CODEC_SR_RFS_N1F0 0x0008 // (FIFO-1, FIFO-0):(NOT FULL, FULL)
#define CC_CODEC_SR_RFS_F1N0 0x0010 // (FIFO-1, FIFO-0):(FULL, NOT FULL)
#define CC_CODEC_SR_RFS_F1F0 0x0018 // (FIFO-1, FIFO-0):(FULL, FULL)
#define CC_CODEC_SR_RFU 0x0004
#define CC_CODEC_SR_RFO 0x0002
#define CC_CODEC_SR_RDI 0x0001
// Frequency Select Register (FSR)
#define CC_CODEC_FSR_FS_8000HZ 0x0000
#define CC_CODEC_FSR_FS_9600HZ 0x0001
#define CC_CODEC_FSR_FS_12000HZ 0x0002
#define CC_CODEC_FSR_FS_16000HZ 0x0003
#define CC_CODEC_FSR_FS_24000HZ 0x0004
#define CC_CODEC_FSR_FS_48000HZ 0x0005
// Command/Status Address Register (CAR/CSAR)
#define CC_CODEC_CAR_RW 0x00080000
// AC97 Transmit Interrupt Enable Register (ATIER)
#define CC_CODEC_ATIER_PLTFRQIE 0x20000000
#define CC_CODEC_ATIER_PRTFRQIE 0x10000000
#define CC_CODEC_ATIER_L1TFRQIE 0x08000000
#define CC_CODEC_ATIER_PCTFRQIE 0x04000000
#define CC_CODEC_ATIER_PLSTFRQIE 0x02000000
#define CC_CODEC_ATIER_PRSTFRQIE 0x01000000
#define CC_CODEC_ATIER_PLFETFRQIE 0x00800000
#define CC_CODEC_ATIER_L2TFRQIE 0x00400000
#define CC_CODEC_ATIER_HTTFRQIE 0x00200000
#define CC_CODEC_ATIER_IOCTFRQIE 0x00100000
#define CC_CODEC_ATIER_PLTFOVIE 0x00080000
#define CC_CODEC_ATIER_PRTFOVIE 0x00040000
#define CC_CODEC_ATIER_L1TFOVIE 0x00020000
#define CC_CODEC_ATIER_PCTFOVIE 0x00010000
#define CC_CODEC_ATIER_PLSTFOVIE 0x00008000
#define CC_CODEC_ATIER_PRSTFOVIE 0x00004000
#define CC_CODEC_ATIER_PLFETFOVIE 0x00002000
#define CC_CODEC_ATIER_L2TFOVIE 0x00001000
#define CC_CODEC_ATIER_HTTFOVIE 0x00000800
#define CC_CODEC_ATIER_IOCTFOVIE 0x00000400
#define CC_CODEC_ATIER_PLTFUNIE 0x00000200
#define CC_CODEC_ATIER_PRTFUNIE 0x00000100
#define CC_CODEC_ATIER_L1TFUNIE 0x00000080
#define CC_CODEC_ATIER_PCTFUNIE 0x00000040
#define CC_CODEC_ATIER_PLSTFUNIE 0x00000020
#define CC_CODEC_ATIER_PRSTFUNIE 0x00000010
#define CC_CODEC_ATIER_PLFETFUNIE 0x00000008
#define CC_CODEC_ATIER_L2TFUNIE 0x00000004
#define CC_CODEC_ATIER_HTTFUNIE 0x00000002
#define CC_CODEC_ATIER_IOCTFUNIE 0x00000001
// AC97 TX FIFO Status Register (ATSR)
#define CC_CODEC_ATSR_PLTFRQ 0x20000000
#define CC_CODEC_ATSR_PRTFRQ 0x10000000
#define CC_CODEC_ATSR_L1TFRQ 0x08000000
#define CC_CODEC_ATSR_PCTFRQ 0x04000000
#define CC_CODEC_ATSR_PLSTFRQ 0x02000000
#define CC_CODEC_ATSR_PRSTFRQ 0x01000000
#define CC_CODEC_ATSR_PLFETFRQ 0x00800000
#define CC_CODEC_ATSR_L2TFRQ 0x00400000
#define CC_CODEC_ATSR_HTTFRQ 0x00200000
#define CC_CODEC_ATSR_IOCTFRQ 0x00100000
#define CC_CODEC_ATSR_PLTFOV 0x00080000
#define CC_CODEC_ATSR_PRTFOV 0x00040000
#define CC_CODEC_ATSR_L1TFOV 0x00020000
#define CC_CODEC_ATSR_PCTFOV 0x00010000
#define CC_CODEC_ATSR_PLSTFOV 0x00008000
#define CC_CODEC_ATSR_PRSTFOV 0x00004000
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