cc.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#define CC_PCMCIA_PSR_BVPP_VCC						0x20	// Enable BVpp 3.3V or 5V
#define CC_PCMCIA_PSR_BVPP_PGM						0x10	// Enable BVpp  12v
#define CC_PCMCIA_PSR_5V_ENBA						0x08	// Enable AVcc 3.3V
#define CC_PCMCIA_PSR_3V_ENBA						0x04	// Enable AVcc   5V
#define CC_PCMCIA_PSR_AVPP_VCC						0x02	// Enable AVpp 3.3V or 5V
#define CC_PCMCIA_PSR_AVPP_PGM						0x01	// Enable AVpp  12V

#define CC_PCMCIA_PSR_AVCC_MASK						0x0c
#define CC_PCMCIA_PSR_AVPP_MASK						0x03
#define CC_PCMCIA_PSR_BVCC_MASK						0xc0
#define CC_PCMCIA_PSR_BVPP_MASK						0x30

#define CC_PCMCIA_PSR_AVCC_AVPP						(CC_PCMCIA_PSR_AVCC_MASK	| CC_PCMCIA_PSR_AVPP_MASK)
#define CC_PCMCIA_PSR_BVCC_BVPP						(CC_PCMCIA_PSR_BVCC_MASK	| CC_PCMCIA_PSR_BVPP_MASK)

//
// definitions for the FIR on the companion chip
//

#define CC_FIR_REGBASE								(HD64465_BASE + HD64465_FIR_OFFSET)

#define CC_FIR_IRRBR_OFFSET							0x0000	// Receiver Buffer Register offset address
#define CC_FIR_IRTBR_OFFSET							0x0000	// Transmitter Buffer Register offset address
#define CC_FIR_IRIER_OFFSET							0x0002	// Interrupt Enable Register offset address
#define CC_FIR_IRIIR_OFFSET							0x0004	// Interrupt Identification Register offset address
#define CC_FIR_IRFCR_OFFSET							0x0004	// FIFO Control Register offset address
#define CC_FIR_IRLCR_OFFSET							0x0006	// Line Control Register offset address
#define CC_FIR_IRMCR_OFFSET							0x0008	// Modem Control Register offset address
#define CC_FIR_IRDLL_OFFSET							0x0000	// Divisor Latch LSB offset address
#define CC_FIR_IRDLM_OFFSET							0x0002	// Divisor Latch MSB offset address
#define CC_FIR_IRLSR_OFFSET							0x000a	// Line Status Register offset address
#define CC_FIR_IRMSR_OFFSET							0x000c	// Modem Status Register offset address
#define CC_FIR_IRSCR_OFFSET							0x000e	// Scratch Pad Register offset address

#define CC_FIR_IMSTCR_OFFSET						0x0100	// Master Control Register offset address
#define CC_FIR_IMSTSR_OFFSET						0x0102	// Master Status Register offset address
#define CC_FIR_IMISCR_OFFSET						0x0102	// Misc. Control Register offset address
#define CC_FIR_IRFR_OFFSET							0x0104	// Rx FIFO Register offset address
#define CC_FIR_ITFR_OFFSET							0x0104	// Tx FIFO Register offset address
#define CC_FIR_ITC1R_OFFSET							0x0106	// Tx Control 1 Register offset address
#define CC_FIR_ITC2R_OFFSET							0x0108	// Tx Control 2 Register offset address
#define CC_FIR_ITSR_OFFSET							0x010a	// Tx Status Register offset address
#define CC_FIR_IRCR_OFFSET							0x010c	// Rx control Register offset address
#define CC_FIR_IRSR_OFFSET							0x010e	// Rx Status Register offset address
#define CC_FIR_IRSTCR_OFFSET						0x010e	// Reset Command Register offset address

#define CC_FIR_IFAR_OFFSET							0x0102	// Frame Address Register offset address
#define CC_FIR_IRBCLR_OFFSET						0x0104	// Rx Byte Count Low Register offset address
#define CC_FIR_IRBCHR_OFFSET						0x0106	// Rx Byte Count High Register offset address
#define CC_FIR_IRRFPLR_OFFSET						0x0108	// Rx Ring Frame Pointer Low Register offset address
#define CC_FIR_IRRFPHR_OFFSET						0x010a	// Rx Ring Frame Pointer High Register offset address
#define CC_FIR_ITBCLR_OFFSET						0x010c	// Tx Byte Count Low Register offset address
#define CC_FIR_ITBCHR_OFFSET						0x010e	// Tx Byte Count High Register offset address

#define CC_FIR_IIRC1R_OFFSET						0x0102	// Infrared Configuration 1 Register offset address
#define CC_FIR_IIRTCR_OFFSET						0x0104	// Infrared Transceiver Control Register offset address
#define CC_FIR_IIRC2R_OFFSET						0x0106	// Infrared Configuration 2 Register offset address
#define CC_FIR_ITMR_OFFSET							0x0108	// Timer Register offset address
#define CC_FIR_IIRC3R_OFFSET						0x010a	// Infrared Configuration 3 Register offset address

#define CC_FIR_DMARP_OFFSET							0x0110	// DMA Data Read Port offset address
#define CC_FIR_DMAWP_OFFSET							0x0110	// DMA Data Write Port offset address
#define CC_FIR_ISIRR_OFFSET							0x0120	// SIR Register offset address
#define CC_FIR_IFIRCR_OFFSET						0x01e0	// FIR Configuration Register offset address
#define CC_FIR_ITMCR_OFFSET							0x01f0	// Timing Control Register offset address

#define CC_FIR_IRRBR								(CC_FIR_REGBASE + CC_FIR_IRRBR_OFFSET)	//Receiver Buffer Register 
#define CC_FIR_IRTBR								(CC_FIR_REGBASE + CC_FIR_IRTBR_OFFSET)	//Transmitter Buffer Register 
#define CC_FIR_IRIER								(CC_FIR_REGBASE + CC_FIR_IRIER_OFFSET)	//Interrupt Enable Register 
#define CC_FIR_IRIIR								(CC_FIR_REGBASE + CC_FIR_IRIIR_OFFSET)	//Interrupt Identification Register 
#define CC_FIR_IRFCR								(CC_FIR_REGBASE + CC_FIR_IRFCR_OFFSET)	//FIFO Control Register 
#define CC_FIR_IRLCR								(CC_FIR_REGBASE + CC_FIR_IRLCR_OFFSET)	//Line Control Register 
#define CC_FIR_IRMCR								(CC_FIR_REGBASE + CC_FIR_IRMCR_OFFSET)	//Modem Control Register 
#define CC_FIR_IRDLL								(CC_FIR_REGBASE + CC_FIR_IRDLL_OFFSET)	//Divisor Latch LSB 
#define CC_FIR_IRDLM								(CC_FIR_REGBASE + CC_FIR_IRDLM_OFFSET)	//Divisor Latch MSB 
#define CC_FIR_IRLSR								(CC_FIR_REGBASE + CC_FIR_IRLSR_OFFSET)	//Line Status Register 
#define CC_FIR_IRMSR								(CC_FIR_REGBASE + CC_FIR_IRMSR_OFFSET)	//Modem Status Register 
#define CC_FIR_IRSCR								(CC_FIR_REGBASE + CC_FIR_IRSCR_OFFSET)	//Scratch Pad Register 

#define CC_FIR_IMSTCR								(CC_FIR_REGBASE + CC_FIR_IMSTCR_OFFSET)	//Master Control Register 
#define CC_FIR_IMSTSR								(CC_FIR_REGBASE + CC_FIR_IMSTSR_OFFSET)	//Master Status Register 
#define CC_FIR_IMISCR								(CC_FIR_REGBASE + CC_FIR_IMISCR_OFFSET)	//Misc. Control Register 
#define CC_FIR_IRFR									(CC_FIR_REGBASE + CC_FIR_IRFR_OFFSET)	//Rx FIFO Register 
#define CC_FIR_ITFR									(CC_FIR_REGBASE + CC_FIR_ITFR_OFFSET)	//Tx FIFO Register 
#define CC_FIR_ITC1R								(CC_FIR_REGBASE + CC_FIR_ITC1R_OFFSET)	//Tx Control 1 Register 
#define CC_FIR_ITC2R								(CC_FIR_REGBASE + CC_FIR_ITC2R_OFFSET)	//Tx Control 2 Register 
#define CC_FIR_ITSR									(CC_FIR_REGBASE + CC_FIR_ITSR_OFFSET)	//Tx Status Register 
#define CC_FIR_IRCR									(CC_FIR_REGBASE + CC_FIR_IRCR_OFFSET)	//Rx control Register 
#define CC_FIR_IRSR									(CC_FIR_REGBASE + CC_FIR_IRSR_OFFSET)	//Rx Status Register 
#define CC_FIR_IRSTCR								(CC_FIR_REGBASE + CC_FIR_IRSTCR_OFFSET)	//Reset Command Register 

#define CC_FIR_IFAR									(CC_FIR_REGBASE + CC_FIR_IFAR_OFFSET)	//Frame Address Register 
#define CC_FIR_IRBCLR								(CC_FIR_REGBASE + CC_FIR_IRBCLR_OFFSET)	//Rx Byte Count Low Register
#define CC_FIR_IRBCHR								(CC_FIR_REGBASE + CC_FIR_IRBCHR_OFFSET)	//Rx Byte Count High Register 
#define CC_FIR_IRRFPLR								(CC_FIR_REGBASE + CC_FIR_IRRFPLR_OFFSET)//Rx Ring Frame Pointer Low Register 
#define CC_FIR_IRRFPHR								(CC_FIR_REGBASE + CC_FIR_IRRFPHR_OFFSET)//Rx Ring Frame Pointer High Register 
#define CC_FIR_ITBCLR								(CC_FIR_REGBASE + CC_FIR_ITBCLR_OFFSET)	//Tx Byte Count Low Register 
#define CC_FIR_ITBCHR								(CC_FIR_REGBASE + CC_FIR_ITBCHR_OFFSET)	//Tx Byte Count High Register 

#define CC_FIR_IIRC1R								(CC_FIR_REGBASE + CC_FIR_IIRC1R_OFFSET)	//Infrared Configuration 1 Register 
#define CC_FIR_IIRTCR								(CC_FIR_REGBASE + CC_FIR_IIRTCR_OFFSET)	//Infrared Transceiver Control Register 
#define CC_FIR_IIRC2R								(CC_FIR_REGBASE + CC_FIR_IIRC2R_OFFSET)	//Infrared Configuration 2 Register 
#define CC_FIR_ITMR									(CC_FIR_REGBASE + CC_FIR_ITMR_OFFSET)	//Timer Register 
#define CC_FIR_IIRC3R								(CC_FIR_REGBASE + CC_FIR_IIRC3R_OFFSET)	//Infrared Configuration 3 Register 

#define CC_FIR_DMARP								(CC_FIR_REGBASE + CC_FIR_DMARP_OFFSET)	//DMA Data Read Port 
#define CC_FIR_DMAWP								(CC_FIR_REGBASE + CC_FIR_DMAWP_OFFSET)	//DMA Data Write Port 
#define CC_FIR_ISIRR								(CC_FIR_REGBASE + CC_FIR_ISIRR_OFFSET)	//SIR Register 
#define CC_FIR_IFIRCR								(CC_FIR_REGBASE + CC_FIR_IFIRCR_OFFSET)	//FIR Configuration Register 
#define CC_FIR_ITMCR								(CC_FIR_REGBASE + CC_FIR_ITMCR_OFFSET)	//Timing Control Register 

//Master Control Register (IMSTCR)
#define CC_FIR_IMSTCR_IEN							0x80
#define CC_FIR_IMSTCR_TXEN							0x40
#define CC_FIR_IMSTCR_RXEN							0x20
#define CC_FIR_IMSTCR_RST_BANK						0xe0
#define CC_FIR_IMSTCR_BANK0							0x00
#define CC_FIR_IMSTCR_BANK1							0x01
#define CC_FIR_IMSTCR_BANK2							0x02

//Master Status Register (IMSTSR)
#define CC_FIR_IMSTSR_TMI							0x40
#define CC_FIR_IMSTSR_TXI							0x20
#define CC_FIR_IMSTSR_RXI							0x10
#define CC_FIR_IMSTSR_IID_RXSC						0x08
#define CC_FIR_IMSTSR_IID_RXDA						0x0a
#define CC_FIR_IMSTSR_IID_TXBE						0x0c
#define CC_FIR_IMSTSR_IID_TXSC						0x0e

//Miscellaneous Control Register (IMISCR)
#define CC_FIR_IMISCR_DCS_TX						0x80
#define CC_FIR_IMISCR_DCS_RX						0x40
#define CC_FIR_IMISCR_DCS_NONE						0x00
#define CC_FIR_IMISCR_ILOOP							0x10

//Tx Control 1 Register(ITC1R)
#define CC_FIR_ITC1R_RTS							0x80
#define CC_FIR_ITC1R_TFRIEN							0x40
#define CC_FIR_ITC1R_TFUIEN							0x20
#define CC_FIR_ITC1R_TFTL							0x10
#define CC_FIR_ITC1R_ADRTS							0x08
#define CC_FIR_ITC1R_ACEOM							0x04
#define CC_FIR_ITC1R_TIDL							0x02
#define CC_FIR_ITC1R_UA								0x01

//Tx Control 2 Register (ITC2R)
#define CC_FIR_ITC2R_SB								0x80
#define CC_FIR_ITC2R_ACRCG							0x40
#define CC_FIR_ITC2R_SIP_NOW						0x20
#define CC_FIR_ITC2R_SIP_AFTER						0x10
#define CC_FIR_ITC2R_NSFP							0x08
#define CC_FIR_ITC2R_EEIL_EOM						0x00
#define CC_FIR_ITC2R_EEIL_16						0x01
#define CC_FIR_ITC2R_EEIL_32						0x02
#define CC_FIR_ITC2R_EEIL_64						0x03
#define CC_FIR_ITC2R_EEIL_128						0x04
#define CC_FIR_ITC2R_EEIL_256						0x05
#define CC_FIR_ITC2R_EEIL_512						0x06
#define CC_FIR_ITC2R_EEIL_1024						0x07

//Tx Status Register (ITSR)
#define CC_FIR_ITSR_TFUR							0x08
#define CC_FIR_ITSR_EOM								0x04
#define CC_FIR_ITSR_TFRDY							0x02
#define CC_FIR_ITSR_EEOM							0x01

//Rx Control Register (IRCR)
#define CC_FIR_IRCR_RFTL							0x80
#define CC_FIR_IRCR_ACRCC							0x40
#define CC_FIR_IRCR_RADM_ALL						0x00
#define CC_FIR_IRCR_RADM_LOHI_FAR					0x10
#define CC_FIR_IRCR_RADM_HI_FAR						0x20
#define CC_FIR_IRCR_SYNIEN							0x08
#define CC_FIR_IRCR_RFRIEN							0x02
#define CC_FIR_IRCR_SCIEN							0x01

//Rx Status Register (IRSR)
#define CC_FIR_IRSR_ABORT							0x80
#define CC_FIR_IRSR_CRCER							0x40
#define CC_FIR_IRSR_RFOVF							0x20
#define CC_FIR_IRSR_EOF								0x10
#define CC_FIR_IRSR_RFEM							0x08
#define CC_FIR_IRSR_SYNC							0x04

//Reset Command Register (IRSTCR)
#define CC_FIR_IRSTCR_RSTC_HUNT						0x10
#define CC_FIR_IRSTCR_RSTC_RXFIFO					0x20
#define CC_FIR_IRSTCR_RSTC_RXSCI					0x30
#define CC_FIR_IRSTCR_RSTC_RXRFP					0x40
#define CC_FIR_IRSTCR_RSTC_UNDERRUN					0x50
#define CC_FIR_IRSTCR_RSTC_TXFIFO					0x60
#define CC_FIR_IRSTCR_RSTC_HW						0x70

//Infrared Configuration 1 Register (IIRC1R)
#define CC_FIR_IIRC1R_IRSPD_1152					0x00
#define CC_FIR_IIRC1R_IRSPD_0756					0x10
#define CC_FIR_IIRC1R_IRSPD_0576					0x10 // lk added - i think it should be 576 (for 57600 baud) instead of 756, but i left both in here because the aspen code is using 756 where as the S1 code is using 576
#define CC_FIR_IIRC1R_IRSPD_0288					0x20
#define CC_FIR_IIRC1R_IRMOD_HPSIR					0x00
#define CC_FIR_IIRC1R_IRMOD_ASK						0x01
#define CC_FIR_IIRC1R_IRMOD_MIR						0x02
#define CC_FIR_IIRC1R_IRMOD_FIR						0x04

//Infrared Transceiver Control Register (IIRTCR)
#define CC_FIR_IIRTCR_DFREQ							0x20
#define CC_FIR_IIRTCR_MODSEL						0x10
#define CC_FIR_IIRTCR_ECHO							0x08
#define CC_FIR_IIRTCR_TXDF							0x02

//Infrared Configuration 2 Register (IIRC2R)
#define CC_FIR_IIRC2R_CHOP_DISABLE					0x70
#define CC_FIR_IIRC2R_CHOP_EX187					0x74
#define CC_FIR_IIRC2R_CHOP_EX229					0x78
#define CC_FIR_IIRC2R_CHOP_EX208					0x7c
#define CC_FIR_IIRC2R_CHOP_ENABLE_MAX				0xf0
#define CC_FIR_IIRC2R_CHOP_ENABLE_LESS				0xf4
#define CC_FIR_IIRC2R_CHOP_ENABLE_ZERO_BTB42		0xf8
#define CC_FIR_IIRC2R_CHOP_ENABLE_ZERO				0xfc
#define CC_FIR_IIRC2R_DSIRI							0x02
#define CC_FIR_IIRC2R_DFIRI							0x01

//Infrared Configuration 3 Register (IIRC3R)
#define CC_FIR_IIRC3R_SCDIEN						0x80
#define CC_FIR_IIRC3R_SCD							0x40
#define CC_FIR_IIRC3R_TMIEN							0x02
#define CC_FIR_IIRC3R_TMI							0x01

//SIR Register (ISIRR)
#define CC_FIR_ISIRR_SLOOP							0x02
#define CC_FIR_ISIRR_SIRMOD							0x01

//FIR Configuration Register (IFIRCR)
#define CC_FIR_IFIRCR_RX2_PP						0x04
#define CC_FIR_IFIRCR_RX_PP							0x02
#define CC_FIR_IFIRCR_TMODE							0x01

//Timing Control Register (ITMCR)
#define CC_FIR_ITMCR_TMCR_12						0x00
#define CC_FIR_ITMCR_TMCR_25						0x02
#define CC_FIR_ITMCR_TMCR_30						0x03
#define CC_FIR_ITMCR_TMCR_40						0x04
#define CC_FIR_ITMCR_TMCR_50						0x05
#define CC_FIR_ITMCR_TMCR_66						0x06


//
// definitions for the UART on the companion chip
//

#define CC_UART_REGBASE								(HD64465_BASE + HD64465_UART_OFFSET)

#define CC_UART_UTBR_OFFSET								0x0000
#define CC_UART_URBR_OFFSET								0x0000	// Mirrors UTBR
#define CC_UART_UIER_OFFSET								0x0002
#define CC_UART_UIIR_OFFSET								0x0004
#define CC_UART_UFCR_OFFSET								0x0004	// Mirrors UIIR
#define CC_UART_ULCR_OFFSET								0x0006
#define CC_UART_UMCR_OFFSET								0x0008
#define CC_UART_UDLL_OFFSET								0x0000
#define CC_UART_UDLM_OFFSET								0x0002
#define CC_UART_ULSR_OFFSET								0x000a
#define CC_UART_UMSR_OFFSET								0x000c
#define CC_UART_USCR_OFFSET								0x000e

#define CC_16550_REG_STRIDE								2				// each register is spaced 2 bytes apart

#define CC_UART_UTBR				(CC_UART_REGBASE + CC_UART_UTBR_OFFSET)
#define CC_UART_URBR				(CC_UART_REGBASE + CC_UART_URBR_OFFSET)