📄 cc.h
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#define CC_GPIO_GPADR (CC_GPIO_REGBASE + CC_GPIO_GPADR_OFFSET) // Port A Data Reg
#define CC_GPIO_GPBDR (CC_GPIO_REGBASE + CC_GPIO_GPBDR_OFFSET) // Port B Data Reg
#define CC_GPIO_GPCDR (CC_GPIO_REGBASE + CC_GPIO_GPCDR_OFFSET) // Port C Data Reg
#define CC_GPIO_GPDDR (CC_GPIO_REGBASE + CC_GPIO_GPDDR_OFFSET) // Port D Data Reg
#define CC_GPIO_GPEDR (CC_GPIO_REGBASE + CC_GPIO_GPEDR_OFFSET) // Port E Data Reg
#define CC_GPIO_GPAICR (CC_GPIO_REGBASE + CC_GPIO_GPAICR_OFFSET) // Port A Interrupt Control Reg
#define CC_GPIO_GPBICR (CC_GPIO_REGBASE + CC_GPIO_GPBICR_OFFSET) // Port B Interrupt Control Reg
#define CC_GPIO_GPCICR (CC_GPIO_REGBASE + CC_GPIO_GPCICR_OFFSET) // Port C Interrupt Control Reg
#define CC_GPIO_GPDICR (CC_GPIO_REGBASE + CC_GPIO_GPDICR_OFFSET) // Port D Interrupt Control Reg
#define CC_GPIO_GPEICR (CC_GPIO_REGBASE + CC_GPIO_GPEICR_OFFSET) // Port E Interrupt Control Reg
#define CC_GPIO_GPAISR (CC_GPIO_REGBASE + CC_GPIO_GPAISR_OFFSET) // Port A Interrupt Status Reg
#define CC_GPIO_GPBISR (CC_GPIO_REGBASE + CC_GPIO_GPBISR_OFFSET) // Port B Interrupt Status Reg
#define CC_GPIO_GPCISR (CC_GPIO_REGBASE + CC_GPIO_GPCISR_OFFSET) // Port C Interrupt Status Reg
#define CC_GPIO_GPDISR (CC_GPIO_REGBASE + CC_GPIO_GPDISR_OFFSET) // Port D Interrupt Status Reg
#define CC_GPIO_GPEISR (CC_GPIO_REGBASE + CC_GPIO_GPEISR_OFFSET) // Port E Interrupt Status Reg
//
// The companion chip interrupt controller
//
#if ENABLE_HD64464!=1
#define CC_INTC_REGBASE_463 (HD64463_BASE + HD64463_INTC_OFFSET)
#endif
#define CC_INTC_REGBASE (HD64465_BASE + HD64465_INTC_OFFSET)
#define CC_INTC_NIRR_OFFSET 0x0000 // Interrupt Request Register Address Offset
#define CC_INTC_NIMR_OFFSET 0x0002 // Interrupt Mask Register Address Offset
#define CC_INTC_NIRR (CC_INTC_REGBASE + CC_INTC_NIRR_OFFSET) // Interrupt Request Register Address Offset
#define CC_INTC_NIMR (CC_INTC_REGBASE + CC_INTC_NIMR_OFFSET)
// Interrupt Request Register (NIRR)
#define CC_INTC_NIRR_PS2KBR 0x8000 /* PS/2 Keyboard interrupt */ /* HD64465 only 99-08-11 cea */
#define CC_INTC_NIRR_PS2MSR 0x0080 /* PS/2 mouse interrupt */ /* HD64465 only 99-08-11 cea */
#define CC_INTC_NIRR_PCC0R 0x4000 // PCC0R interrupt
#define CC_INTC_NIRR_PCC1R 0x2000 // PCC1R interrupt
#define CC_INTC_NIRR_AFER 0x1000 // AFER interrupt
#define CC_INTC_NIRR_GPIOR 0x0800 // GPIOR interrupt
#define CC_INTC_NIRR_TMU0R 0x0400 // TMU0R interrupt
#define CC_INTC_NIRR_TMU1R 0x0200 // TMU1R interrupt
#define CC_INTC_NIRR_KBCR 0x0100 // KBDR interrupt
#define CC_INTC_NIRR_IRDAR 0x0040 // IRDAR interrupt
#define CC_INTC_NIRR_UART0R 0x0020 // UART0R interrupt
#define CC_INTC_NIRR_UART1R 0x0010 // UART1R interrupt (not available in HD64465)
#define CC_INTC_NIRR_PPR 0x0008 // PPR interrupt
#define CC_INTC_NIRR_SCDIR 0x0004 // SCDIR interrupt
#define CC_INTC_NIRR_USBR 0x0002 // USBR interrupt
#define CC_INTC_NIRR_ADCR 0x0001 // ADCR interrupt
// Interrupt Mask Register (NIMR)
#define CC_INTC_NIMR_ALL_MASK 0xffff // all interrupt mask
#define CC_INTC_NIMR_PS2KBM_MASK 0x8000 /* PS/2 Keyboard mask */ /* HD64465 only 99-08-11 cea */
#define CC_INTC_NIMR_PS2MSM_MASK 0x0080 /* PS/2 mouse mask */ /* HD64465 only 99-08-11 cea */
#define CC_INTC_NIMR_PCC0M_MASK 0x4000 // PCC0M interrupt mask
#define CC_INTC_NIMR_PCC1M_MASK 0x2000 // PCC1M interrupt mask
#define CC_INTC_NIMR_AFEM_MASK 0x1000 // AFEM interrupt mask
#define CC_INTC_NIMR_GPIOM_MASK 0x0800 // GPIOM interrupt mask
#define CC_INTC_NIMR_TMU0M_MASK 0x0400 // TMU0M interrupt mask
#define CC_INTC_NIMR_TMU1M_MASK 0x0200 // TMU1M interrupt mask
#define CC_INTC_NIMR_KBCM_MASK 0x0100 // KBDM interrupt mask
#define CC_INTC_NIMR_IRDAM_MASK 0x0040 // IRDAM interrupt mask
#define CC_INTC_NIMR_UART0M_MASK 0x0020 // UART0M interrupt mask
#define CC_INTC_NIMR_UART1M_MASK 0x0010 // UART1M interrupt mask
#define CC_INTC_NIMR_PPM_MASK 0x0008 // PPM interrupt mask
#define CC_INTC_NIMR_SCDIM_MASK 0x0004 // SCDIM interrupt mask
#define CC_INTC_NIMR_USBM_MASK 0x0002 // USBM interrupt mask
#define CC_INTC_NIMR_ADCM_MASK 0x0001 // ADCM interrupt mask
#define CC_INTC_NIMR_PS2KBM_UNMASK 0x7FFF /* PS/2 Keyboard UNmask */ /* HD64465 only 99-08-11 cea */
#define CC_INTC_NIMR_PS2MSM_UNMASK 0xFF7F /* PS/2 mouse UNmask */ /* HD64465 only 99-08-11 cea */
#define CC_INTC_NIMR_PCC0M_UNMASK 0xbfff // PCC0M interrupt unmask
#define CC_INTC_NIMR_PCC1M_UNMASK 0xdfff // PCC1M interrupt unmask
#define CC_INTC_NIMR_AFEM_UNMASK 0xefff // AFEM interrupt unmask
#define CC_INTC_NIMR_GPIOM_UNMASK 0xf7ff // GPIOM interrupt unmask
#define CC_INTC_NIMR_TMU0M_UNMASK 0xfbff // TMU0M interrupt unmask
#define CC_INTC_NIMR_TMU1M_UNMASK 0xfdff // TMU1M interrupt unmask
#define CC_INTC_NIMR_KBCM_UNMASK 0xfeff // KBDM interrupt unmask
#define CC_INTC_NIMR_IRDAM_UNMASK 0xffbf // IRDAM interrupt unmask
#define CC_INTC_NIMR_UART0M_UNMASK 0xffdf // UART0M interrupt unmask
#define CC_INTC_NIMR_UART1M_UNMASK 0xffef // UART1M interrupt unmask
#define CC_INTC_NIMR_PPM_UNMASK 0xfff7 // PPM interrupt unmask
#define CC_INTC_NIMR_SCDIM_UNMASK 0xfffb // SCDIM interrupt unmask
#define CC_INTC_NIMR_USBM_UNMASK 0xfffd // USBM interrupt unmask
#define CC_INTC_NIMR_ADCM_UNMASK 0xfffe // ADCM interrupt unmask
//
// definitions of Timer interface (TMR) on the companion chip
// all the timer registers are 16 bits wide
//
#if ENABLE_HD64464!=1
#define CC_TMR_REGBASE_463 (HD64463_BASE + HD64463_TMR_OFFSET)
#endif
#define CC_TMR_REGBASE (HD64465_BASE + HD64465_TMR_OFFSET)
#define CC_TMR_TCVR1_OFFSET 0x0000 // Constant 1 Offset Address
#define CC_TMR_TCVR0_OFFSET 0x0002 // Constant 0 Offset Address
#define CC_TMR_TRVR1_OFFSET 0x0004 // Read Count 1 Offset Address
#define CC_TMR_TRVR0_OFFSET 0x0006 // Read Count 0 Offset Address
#define CC_TMR_TCR1_OFFSET 0x0008 // Control 1 Offset Address
#define CC_TMR_TCR0_OFFSET 0x000A // Control 0 Offset Address
#define CC_TMR_TIRR_OFFSET 0x000C // Interrupt Request Offset Address
#define CC_TMR_TIDR_OFFSET 0x000E // Interrupt Disable Offset Address
#define CC_TMR_REGSIZE 0x0010 // total size of TMR regs in CC ASIC
#define CC_TMR_TCVR1 (CC_TMR_REGBASE + CC_TMR_TCVR1_OFFSET) // Constant 1
#define CC_TMR_TCVR0 (CC_TMR_REGBASE + CC_TMR_TCVR0_OFFSET) // Constant 0
#define CC_TMR_TRVR1 (CC_TMR_REGBASE + CC_TMR_TRVR1_OFFSET) // Read Count 1
#define CC_TMR_TRVR0 (CC_TMR_REGBASE + CC_TMR_TRVR0_OFFSET) // Read Count 0
#define CC_TMR_TCR1 (CC_TMR_REGBASE + CC_TMR_TCR1_OFFSET) // Control 1
#define CC_TMR_TCR0 (CC_TMR_REGBASE + CC_TMR_TCR0_OFFSET) // Control 0
#define CC_TMR_TIRR (CC_TMR_REGBASE + CC_TMR_TIRR_OFFSET) // Interrupt Request
#define CC_TMR_TIDR (CC_TMR_REGBASE + CC_TMR_TIDR_OFFSET) // Interrupt Mask
// Timer 1 Control Register (TCR1)
#define CC_TMR_TCR1_EDMA 0x0010
#define CC_TMR_TCR1_ETMO1 0x0008
#define CC_TMR_TCR1_PST1_CKIO 0x0006
#define CC_TMR_TCR1_PST1_CKIO_DIVID_4 0x0004
#define CC_TMR_TCR1_PST1_CKIO_DIVID_8 0x0002
#define CC_TMR_TCR1_PST1_CKIO_DIVID_16 0x0000
#define CC_TMR_TCR1_T1STP 0x0001
// Timer 0 Control Register (TCR1)
#define CC_TMR_TCR0_EADT 0x0010
#define CC_TMR_TCR0_ETMO0 0x0008
#define CC_TMR_TCR0_PST0_CKIO 0x0006
#define CC_TMR_TCR0_PST0_CKIO_DIVID_4 0x0004
#define CC_TMR_TCR0_PST0_CKIO_DIVID_8 0x0002
#define CC_TMR_TCR0_PST0_CKIO_DIVID_16 0x0000
#define CC_TMR_TCR0_T0STP 0x0001
// Timer Interrupt Request Register (TIRR)
#define CC_TMR_TIRR_TMU1R 0x0002
#define CC_TMR_TIRR_TMU0R 0x0001
// Timer Interrupt Disable Register (TIDR)
#define CC_TMR_TIRR_TMU1D 0x0002
#define CC_TMR_TIRR_TMU0D 0x0001
//
// PCMCIA defines
//
#if ENABLE_HD64464!=1
#define CC_PCMCIA_REGBASE_463 (HD64463_BASE + HD64463_PCMCIA_OFFSET)
#endif
#define CC_PCMCIA_REGBASE (HD64465_BASE + HD64465_PCMCIA_OFFSET)
// Card 0 defines
#define CC_PCMCIA_PCC0ISR_OFFSET 0x0000 // Interface Status Register offset address
#define CC_PCMCIA_PCC0GCR_OFFSET 0x0002 // General Control Register offset address
#define CC_PCMCIA_PCC0CSCR_OFFSET 0x0004 // Status Change Register offset address
#define CC_PCMCIA_PCC0CSCIER_OFFSET 0x0006 // Status Change Int. En reg offset address
#define CC_PCMCIA_PCC0SCR_OFFSET 0x0008 // Software Control reg offset address
#define CC_PCMCIA_PCCPSR_OFFSET 0x000a // Serial Power Switch Control reg offset address
#define CC_PCMCIA_PCC0ISR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0ISR_OFFSET) // Interface Status Register
#define CC_PCMCIA_PCC0GCR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0GCR_OFFSET) // General Control Register
#define CC_PCMCIA_PCC0CSCR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0CSCR_OFFSET) // Status Change Register
#define CC_PCMCIA_PCC0CSCIER (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0CSCIER_OFFSET) // Status Change Int. En reg
#define CC_PCMCIA_PCC0SCR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC0SCR_OFFSET) // Software Control reg
#define CC_PCMCIA_PCCPSR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCCPSR_OFFSET) // Serial Power Switch Control reg
// Card 1 defines
#define CC_PCMCIA_PCC1ISR_OFFSET 0x0010 // Interface Status Register
#define CC_PCMCIA_PCC1GCR_OFFSET 0x0012 // General Control Register
#define CC_PCMCIA_PCC1CSCR_OFFSET 0x0014 // Status Change Register
#define CC_PCMCIA_PCC1CSCIER_OFFSET 0x0016 // Status Change Int. En reg
#define CC_PCMCIA_PCC1SCR_OFFSET 0x0018 // Software Control reg
#define CC_PCMCIA_PCC1ISR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1ISR_OFFSET) // Interface Status Register
#define CC_PCMCIA_PCC1GCR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1GCR_OFFSET) // General Control Register
#define CC_PCMCIA_PCC1CSCR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1CSCR_OFFSET) // Status Change Register
#define CC_PCMCIA_PCC1CSCIER (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1CSCIER_OFFSET) // Status Change Int. En reg
#define CC_PCMCIA_PCC1SCR (CC_PCMCIA_REGBASE + CC_PCMCIA_PCC1SCR_OFFSET) // Software Control reg
#define CC_PCMCIA_REGSIZE 0x0020 // as far as these regs can go
// Interface Status Reg
#define CC_PCMCIA_ISR_IREQ_MASK 0x80 // mask to obtain value of IREQ pin
#define CC_PCMCIA_ISR_RDY_MASK 0x80 // mask to obtain value of RDY pin
#define CC_PCMCIA_ISR_WP_MASK 0x40 // mask to obtain value of WP pin
#define CC_PCMCIA_ISR_VS_MASK 0x30 // mask to obtain value of VS1 and VS2
#define CC_PCMCIA_ISR_VS2_MASK 0x20 // mask to obtain value of VS2
#define CC_PCMCIA_ISR_VS1_MASK 0x10 // mask to obtain value of VS1
#define CC_PCMCIA_ISR_CD_MASK 0x0C // mask to obtain value of CD1 and CD2
#define CC_PCMCIA_ISR_CD2_MASK 0x08 // mask to obtain value of CD2
#define CC_PCMCIA_ISR_CD1_MASK 0x04 // mask to obtain value of CD1
#define CC_PCMCIA_ISR_BVD_MASK 0x03 // mask to obtain value of BVD pins
#define CC_PCMCIA_ISR_BVD_NORMAL 0x03 // battery is fine
#define CC_PCMCIA_ISR_BVD_LOW_GD 0x01 // battery is low but data is OK
#define CC_PCMCIA_ISR_BVD_LOW_CD 0x02 // battery is low and data is corrupt
#define CC_PCMCIA_ISR_BVD_DEAD 0x00 // battery is dead
#define CC_PCMCIA_ISR_SPKR_MASK 0x02 // mask to obtain value of SPK pin
#define CC_PCMCIA_ISR_STSCH_MASK 0x01 // mask to obtain value of STSCH pin
// General Control reg
#define CC_PCMCIA_GCR_DRV_ENABLE 0x80 // Enables the PCMCIA card
#define CC_PCMCIA_GCR_RESET 0x40 // Causes a reset on the card
#define CC_PCMCIA_GCR_IO_CARD 0x20 // There is an I/O card in this slot
#define CC_PCMCIA_GCR_MEM_CARD 0x00 // There is a mem card in this slot
#define CC_PCMCIA_GCR_5V_ENABLE 0x10 // Spcifies to use 3.3V
#define CC_PCMCIA_GCR_MMOD_32 0x00 // set mode as 32MB mem areas
#define CC_PCMCIA_GCR_MMOD_16 0x08 // set mode as 16MB mem areas
#define CC_PCMCIA_GCR_A25_HIGH 0x04 // set A25 High
#define CC_PCMCIA_GCR_A25_LOW 0x00 // set A25 Low
#define CC_PCMCIA_GCR_A24_HIGH 0x02 // set A24 High
#define CC_PCMCIA_GCR_A24_LOW 0x00 // set A24 Low
#define CC_PCMCIA_GCR_ADDR_MASK 0x06 // Mask A24 and A25
#define CC_PCMCIA_GCR_REG_HIGH 0x01 // set REG High
#define CC_PCMCIA_GCR_REG_LOW 0x00 // set REG Low
// Card Status Change (PCC0CSCR) Reg
#define CC_PCMCIA_CSCR_GEN_CD_INT 0x80 // Generate a CD interrupt
#define CC_PCMCIA_CSCR_IREQ_INT_REQ 0x20 // IREQ Int has occurred
#define CC_PCMCIA_CSCR_STSCH_INT_REQ 0x10 // STSCH Int has occurred
#define CC_PCMCIA_CSCR_CD_INT_REQ 0x08 // CD Int occurred
#define CC_PCMCIA_CSCR_RDY_INT_REQ 0x04 // RDY Int occurred
#define CC_PCMCIA_CSCR_BW_INT_REQ 0x02 // Batt warning int occurred
#define CC_PCMCIA_CSCR_BE_INT_REQ 0x01 // Batt dead int occurred
#define CC_PCMCIA_CSCR_TPS2206_SEL 0x40 // TPS2206 serial power switch
#define CC_PCMCIA_CSCR_MIC2563_SEL 0xbf // MIC2563 select
// Card Status Change Interrupt Enable Reg
#define CC_PCMCIA_CSCIER_AUTO_GCR 0x80 // Automatically init the GCR
#define CC_PCMCIA_CSCIER_IREQ_DIS 0x00 // Disable IREQ ints
#define CC_PCMCIA_CSCIER_IREQ_LEVEL 0x20 // IREQ Level ints
#define CC_PCMCIA_CSCIER_IREQ_PFE 0x40 // IREQ Falling Edge, Pulse
#define CC_PCMCIA_CSCIER_IREQ_PRE 0x60 // IREQ Rising Edge Pulse
#define CC_PCMCIA_CSCIER_IREQ_MASK 0x60 // For masking this value
#define CC_PCMCIA_CSCIER_STSCH_INT_EN 0x10 // Enable STSCH Interrupts
#define CC_PCMCIA_CSCIER_CD_INT_EN 0x08 // Enable CD Interrupts
#define CC_PCMCIA_CSCIER_RDY_INT_EN 0x04 // Enable RDY/BSY Interrupts
#define CC_PCMCIA_CSCIER_BWE_INT_EN 0x02 // Enable Batt Warning Interrupts
#define CC_PCMCIA_CSCIER_BDE_INT_EN 0x01 // Enable Batt Dead Interrupts
// Software control reg
#define CC_PCMCIA_SCR_3V_ENABLE 0x02 // Specifies to use 5V
#define CC_PCMCIA_SCR_MASK_VCC 0x0c // Masks out our bits
#define CC_PCMCIA_SCR_VCC0VPP0 0x04 // Voltage control pin P0VPP0
#define CC_PCMCIA_SCR_VCC0VPP1 0x08 // Voltage control pin P0VPP1
#define CC_PCMCIA_SCR_VCC1VPP0 0x04 // Voltage control pin P1VPP0
#define CC_PCMCIA_SCR_VCC1VPP1 0x08 // Voltage control pin P1VPP1
#define CC_PCMCIA_SCR_SHDN_ENB 0x10 // Shutdown bit for TPS2206
// Serial Power Switch Control Register
#define CC_PCMCIA_PSR_3V_ENBB 0x80 // Enable BVcc 5V
#define CC_PCMCIA_PSR_5V_ENBB 0x40 // Enable BVcc 3.3V
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