cc.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*

  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.

	Module Name:

		cc.h

	Revision History:

		26th April 1999		Released
		25th May   1999		Added FIR definitions
		14th June  1999		Added HD64464's definitions
		28th June  1999		Fixed minor bug
		11th August1999		Add some HD64465 definitions

*/

#ifndef _CC_H_
#define _CC_H_

// Companion Chip (HD64465) module offsets

#define HD64465_STB_SYSTEM_OFFSET					0x0000		// Power down modes & system configuration
#define HD64465_RESERVED							0x1000		// Reserved
#define HD64465_PCMCIA_OFFSET						0x2000		// PCMCIA
#define HD64465_AFE_OFFSET							0x3000		// Modem analog front end
#define HD64465_GPIO_OFFSET							0x4000		// I/O ports
#define HD64465_INTC_OFFSET							0x5000		// Interrupt Controller
#define HD64465_TMR_OFFSET							0x6000		// Timer
#define HD64465_FIR_OFFSET							0x7000		// IrDA/16550(A) UART
#define HD64465_UART_OFFSET							0x8000		// 16550(B) UART
#define HD64465_EMBEDED_SDRAM_OFFSET				0x9000		// Embeded SDRAM
#define HD64465_PARALLEL_OFFSET						0xA000		// Parallel Port
#define HD64465_USB_OFFSET							0xB000		// USB Host Controller
#define HD64465_CODEC_OFFSET						0xC000		// Serial CODEC Interface
#define HD64465_KBC_OFFSET							0xD000		// Keyboard Controller Interface
#define HD64465_ADC_OFFSET							0xE000		// A/D Converter

#if ENABLE_HD64464!=1
// Companion Chip (HD64463) module offsets
#define HD64463_STB_SYSTEM_OFFSET					0x0000		// Power down modes & system configuration 
#define HD64463_LCDC_OFFSET							0x1000		// LCD/CRT 
#define HD64463_PCMCIA_OFFSET						0x2000		// PCMCIA 
#define HD64463_AFE_OFFSET							0x3000		// Modem analog front end 
#define HD64463_GPIO_OFFSET							0x4000		// I/O ports 	
#define HD64463_INTC_OFFSET							0x5000		// Interrupt Controller 
#define HD64463_TMR_OFFSET							0x6000		// Timer 
#define HD64463_FIR_OFFSET							0x7000		// IrDA/16550(A) UART 
#define HD64463_UART0_OFFSET						0x8000		// 16550(B) UART  
#define HD64463_UART1_OFFSET						0x9000		// Embeded SDRAM 
#define HD64463_PARALLEL_OFFSET						0xA000		// Parallel Port 
#define HD64463_USB_OFFSET							0xB000		// USB Host Controller 
#define HD64463_CODEC_OFFSET						0xC000		// Serial CODEC Interface 
#define HD64463_KBC_OFFSET							0xD000		// Keyboard Controller Interface 
#define HD64463_ADC_OFFSET							0xE000		// A/D Converter 
#endif

//
// definitions of System control and power interface (SYS) on the companion chip ( all the system registers are 16 bits wide )
//

#if ENABLE_HD64464!=1
#define CC_SYS_REGBASE_463							(HD64463_BASE + HD64463_STB_SYSTEM_OFFSET)
#endif

#define CC_SYS_REGBASE								(HD64465_BASE + HD64465_STB_SYSTEM_OFFSET)

#define CC_SYS_SMSCR_OFFSET							0x0000
#define CC_SYS_SCONFR_OFFSET						0x0002
#define CC_SYS_SBCR_OFFSET							0x0004
#define CC_SYS_SPCCR_OFFSET							0x0006
#define CC_SYS_SPSRCR_OFFSET						0x0008
#define CC_SYS_SPLLCR_OFFSET						0x000a
#define CC_SYS_SRR_OFFSET							0x000c
#define CC_SYS_STMCR_OFFSET							0x000e
#define CC_SYS_SDID_OFFSET							0x0010
#define CC_SYS_SDPR_OFFSET							0x0ff0

#define CC_SYS_REGSIZE								0x0ff2			// total size of SYSTEM regs in CC ASIC

#define CC_SYS_SMSCR								(CC_SYS_REGBASE + CC_SYS_SMSCR_OFFSET)
#define CC_SYS_SCONFR								(CC_SYS_REGBASE + CC_SYS_SCONFR_OFFSET)
#define CC_SYS_SBCR									(CC_SYS_REGBASE + CC_SYS_SBCR_OFFSET)
#define CC_SYS_SPCCR								(CC_SYS_REGBASE + CC_SYS_SPCCR_OFFSET)
#define CC_SYS_SPSRCR								(CC_SYS_REGBASE + CC_SYS_SPSRCR_OFFSET)
#define CC_SYS_SPLLCR								(CC_SYS_REGBASE + CC_SYS_SPLLCR_OFFSET)
#define CC_SYS_SRR									(CC_SYS_REGBASE + CC_SYS_SRR_OFFSET)
#define CC_SYS_STMCR								(CC_SYS_REGBASE + CC_SYS_STMCR_OFFSET)
#define CC_SYS_SDID									(CC_SYS_REGBASE + CC_SYS_SDID_OFFSET)
#define CC_SYS_SDPR									(CC_SYS_REGBASE + CC_SYS_SDPR_OFFSET)

// System Module Standby Control Register (SMSCR)

#define CC_SYS_SMSCR_LCDST							0x2000			// HD64463 only
#define CC_SYS_SMSCR_UART0ST						0x0800			// HD64463 only
#define CC_SYS_SMSCR_UART1ST						0x0400			// HD64463 only
#define CC_SYS_SMSCR_USBST							0x0080			// HD64463 only

#define CC_SYS_SMSCR_PS2ST							(0x4000) /* HD64465 only 99-08-11 cea */
#define CC_SYS_SMSCR_ADCST							0x1000
#define CC_SYS_SMSCR_UARTST							0x0800
#define CC_SYS_SMSCR_SCDIST							0x0200
#define CC_SYS_SMSCR_PPST							0x0100
#define CC_SYS_SMSCR_PC0ST							0x0040
#define CC_SYS_SMSCR_PC1ST							0x0020
#define CC_SYS_SMSCR_AFEST							0x0010
#define CC_SYS_SMSCR_TM0ST							0x0008
#define CC_SYS_SMSCR_TM1ST							0x0004
#define CC_SYS_SMSCR_IRDAST							0x0002
#define CC_SYS_SMSCR_KBCST							0x0001

// System Configuration Register (SCONFR)

#define CC_SYS_SCONFR_SLS							0x2000			// HD64463 only
#define CC_SYS_SCONFR_LCDCD_DIVID_3					0x0080			// HD64463 only
#define CC_SYS_SCONFR_LCDCD_DIVID_2					0x0040			// HD64463 only
#define CC_SYS_SCONFR_LCDCD_DIVID_1					0x0000			// HD64463 only
#define CC_SYS_SCONFR_ILCDMS						0x0020			// HD64463 only

#define CC_SYS_SCONFR_HWEN							0x1000
#define CC_SYS_SCONFR_HW1							0x0100
#define CC_SYS_SCONFR_HW2							0x0200
#define CC_SYS_SCONFR_HW3							0x0300
#define CC_SYS_SCONFR_HW4							0x0400
#define CC_SYS_SCONFR_HW5							0x0500
#define CC_SYS_SCONFR_HW6							0x0600
#define CC_SYS_SCONFR_HW7							0x0700
#define CC_SYS_SCONFR_HW8							0x0800
#define CC_SYS_SCONFR_HW9							0x0900
#define CC_SYS_SCONFR_HW10							0x0a00
#define CC_SYS_SCONFR_HW11							0x0b00
#define CC_SYS_SCONFR_HW12							0x0c00
#define CC_SYS_SCONFR_HW13							0x0d00
#define CC_SYS_SCONFR_HW14							0x0e00
#define CC_SYS_SCONFR_HW15							0x0f00

#define CC_SYS_SCONFR_USBCKS						0x0020
#define CC_SYS_SCONFR_SCDICKS						0x0010

#define CC_SYS_SCONFR_PPFMS_ECP_EPP					0x000b
#define CC_SYS_SCONFR_PPFMS_ECP						0x0008
#define CC_SYS_SCONFR_PPFMS_EPP						0x0004
#define CC_SYS_SCONFR_PPFMS_SPP						0x0000

#define CC_SYS_SCONFR_KBWUP							0x0002

// System Bus Control Register (SBCR)

#define CC_SYS_SBCR_LCDIG							0x0080			// HD64463 only

#define CC_SYS_SBCR_PDOF							0x8000			// HD64465 only
#define CC_SYS_SBCR_PDIG							0x4000			// HD64465 only
#define CC_SYS_SBCR_PCOF							0x2000			// HD64465 only
#define CC_SYS_SBCR_PCIG							0x1000			// HD64465 only
#define CC_SYS_SBCR_PBOF							0x0800
#define CC_SYS_SBCR_PBIG							0x0400
#define CC_SYS_SBCR_PAOF							0x0200
#define CC_SYS_SBCR_PAIG							0x0100
#define CC_SYS_SBCR_CSPE							0x0040
#define CC_SYS_SBCR_CMDPE							0x0020
#define CC_SYS_SBCR_ADDRPE							0x0010
#define CC_SYS_SBCR_DATAPE							0x0008
#define CC_SYS_SBCR_CPUBIG							0x0004
#define CC_SYS_SBCR_PEOF							0x0002			// HD64465 only
#define CC_SYS_SBCR_PEIG							0x0001			// HD64465 only

// SYSTEM Peripheral Clock Control Register

#define CC_SYS_SPCCR_URT1CLK						0x4000			// HD64463 only
#define CC_SYS_SPCCR_URT0CLK						0x2000			// HD64463 only
#define CC_SYS_SPCCR_LCKOSC							0x0004			// HD64463 only

#define CC_SYS_SPCCR_ADCCLK							0x8000
#define CC_SYS_SPCCR_UARTCLK						0x2000
#define CC_SYS_SPCCR_PPCLK							0x1000
#define CC_SYS_SPCCR_FIRCLK							0x0800
#define CC_SYS_SPCCR_SIRCLK							0x0400
#define CC_SYS_SPCCR_SCDICLK						0x0200
#define CC_SYS_SPCCR_KBCCLK							0x0100
#define CC_SYS_SPCCR_USBCLK							0x0080
#define CC_SYS_SPCCR_AFECLK							0x0040
#define CC_SYS_SPCCR_UCKOSC							0x0002
#define CC_SYS_SPCCR_AFEOSC							0x0001

// System Peripheral S/W Reset Control Register (SPSRCR)

#define CC_SYS_SPSRCR_LCDCSRT						0x2000			// HD64463 only
#define CC_SYS_SPSRCR_UR0SRT						0x0800			// HD64463 only
#define CC_SYS_SPSRCR_UR1SRT						0x0400			// HD64463 only

#define CC_SYS_SPSRCR_SPORST						0x8000
#define CC_SYS_SPSRCR_ADCSRT						0x1000
#define CC_SYS_SPSRCR_UARTSRT						0x0800
#define CC_SYS_SPSRCR_SCDISRT						0x0200
#define CC_SYS_SPSRCR_PPSRT							0x0100
#define CC_SYS_SPSRCR_USBSRT						0x0080
#define CC_SYS_SPSRCR_PC0SRT						0x0040
#define CC_SYS_SPSRCR_PC1RST						0x0020
#define CC_SYS_SPSRCR_AFERST						0x0010
#define CC_SYS_SPSRCR_TM0RST						0x0008
#define CC_SYS_SPSRCR_TM1RST						0x0004
#define CC_SYS_SPSRCR_IRDARST						0x0002
#define CC_SYS_SPSRCR_KBCRST						0x0001

// System PLL Control Register (SPLLCR)

#define CC_SYS_SPLLCR_PLL2SB						0x0020
#define CC_SYS_SPLLCR_PLL1SB						0x0010
#define CC_SYS_SPLLCR_PLL2BP						0x0002
#define CC_SYS_SPLLCR_PLL1BP						0x0001

// System Test Mode Control Register (STMCR)

#define CC_SYS_STMCR_DITST							0x0400
#define CC_SYS_STMCR_DOTST							0x0200
#define CC_SYS_STMCR_AFETST							0x0100
#define CC_SYS_STMCR_PCITST							0x0080
#define CC_SYS_STMCR_SDBST							0x0040
#define CC_SYS_STMCR_USBST							0x0020
#define CC_SYS_STMCR_PLL2TST						0x0010
#define CC_SYS_STMCR_PLL1TST						0x0008
#define CC_SYS_STMCR_URTTST							0x0004
#define CC_SYS_STMCR_ACTST							0x0002
#define CC_SYS_STMCR_DCTST							0x0001

//
// GPIO regs
//

#if ENABLE_HD64464!=1
#define CC_GPIO_REGBASE_463							(HD64463_BASE + HD64463_GPIO_OFFSET)
#endif

#define CC_GPIO_REGBASE								(HD64465_BASE + HD64465_GPIO_OFFSET)

#define CC_GPIO_GPACR_OFFSET						0x0000	// Port A Control Reg Offset Address 
#define CC_GPIO_GPBCR_OFFSET						0x0002	// Port B Control Reg Offset Address 
#define CC_GPIO_GPCCR_OFFSET						0x0004	// Port C Control Reg Offset Address 
#define CC_GPIO_GPDCR_OFFSET						0x0006	// Port D Control Reg Offset Address 
#define CC_GPIO_GPECR_OFFSET						0x0008	// Port E Control Reg Offset Address 

#define CC_GPIO_GPADR_OFFSET						0x0010	// Port A Data Reg Offset Address 
#define CC_GPIO_GPBDR_OFFSET						0x0012	// Port B Data Reg Offset Address 
#define CC_GPIO_GPCDR_OFFSET						0x0014	// Port C Data Reg Offset Address 
#define CC_GPIO_GPDDR_OFFSET						0x0016	// Port D Data Reg Offset Address 
#define CC_GPIO_GPEDR_OFFSET						0x0018	// Port E Data Reg Offset Address 

#define CC_GPIO_GPAICR_OFFSET						0x0020	// Port A Interrupt Control Reg Offset Address 
#define CC_GPIO_GPBICR_OFFSET						0x0022	// Port B Interrupt Control Reg Offset Address 
#define CC_GPIO_GPCICR_OFFSET						0x0024	// Port C Interrupt Control Reg Offset Address 
#define CC_GPIO_GPDICR_OFFSET						0x0026	// Port D Interrupt Control Reg Offset Address 
#define CC_GPIO_GPEICR_OFFSET						0x0028	// Port E Interrupt Control Reg Offset Address 
	
#define CC_GPIO_GPAISR_OFFSET						0x0040	// Port A Interrupt Status Reg Offset Address 
#define CC_GPIO_GPBISR_OFFSET						0x0042	// Port B Interrupt Status Reg Offset Address 
#define CC_GPIO_GPCISR_OFFSET						0x0044	// Port C Interrupt Status Reg Offset Address 
#define CC_GPIO_GPDISR_OFFSET						0x0046	// Port D Interrupt Status Reg Offset Address 
#define CC_GPIO_GPEISR_OFFSET						0x0048	// Port E Interrupt Status Reg Offset Address 

#define CC_GPIO_REGSIZE								0x0050

#define CC_GPIO_GPACR								(CC_GPIO_REGBASE + CC_GPIO_GPACR_OFFSET)	// Port A Control Reg 
#define CC_GPIO_GPBCR								(CC_GPIO_REGBASE + CC_GPIO_GPBCR_OFFSET)	// Port B Control Reg 
#define CC_GPIO_GPCCR								(CC_GPIO_REGBASE + CC_GPIO_GPCCR_OFFSET)	// Port C Control Reg 
#define CC_GPIO_GPDCR								(CC_GPIO_REGBASE + CC_GPIO_GPDCR_OFFSET)	// Port D Control Reg 
#define CC_GPIO_GPECR								(CC_GPIO_REGBASE + CC_GPIO_GPECR_OFFSET)	// Port E Control Reg