ecpreg.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-1998  Microsoft Corporation

Module Name:  

ecpreg.h

Abstract:

1284 ECP hardware registers definitions

Notes: 


--*/

// Register definitions of ECP hardware
#define ECP_Data                0x000           // Mode 000, 001, parallel port data
#define ECP_AFifo               0x000           // Mode 011, ecp fifo-addressRLE
#define ECP_DSR_Reg             0x001           // Device Status register
#define ECP_DCR_Reg             0x002           // Device Control register
#define ECP_CFifo               0x400           // Mode 010, parallel port data Fifo
#define ECP_DFifo               0x400           // Mode 011, ECP data Fifo
#define ECP_TFifo               0x400           // Mode 110, Test mode
#define ECP_CONFG_A             0x400           // Mode 111, configuration A
#define ECP_CONFG_B             0x401           // Mode 111, configuration B
#define ECP_ECR_Reg             0x402           // Extended Control register

// ECR register definitions of ECP hardware
#define ECP_ECP_MODE    0x74        // ECP H/W assisted ECP protocol
#define ECP_STD_MODE    0x14        // 0001 0100 standard centronic mode
#define ECP_PS2_MODE    0x34        // 0011 0100 ps/2 centronic mode
#define ECP_TEST_MODE   0xD4        // 1101 0100 test mode
#define ECP_CONFG_MODE  0xF4        // 1111 0100 configuration mode
#define ECP_FIFO_MODE   0x54        // 0101 0100 parallel FIFO mode

// ECR register mode change without effecting other bits
#define ECP_STD_ONLY         0x1F    // 0001 1111

// ECR dmaEn bit mask and value
#define ECP_ECR_DMAEN_BIT             0x08
#define ECP_ECR_DMAEN_BIT_MASK        0xF7

// ECR serviceIntr bit mask and value
#define ECP_ECR_SERVICE_INT_BIT       0x04    // mask out serviceIntr bit
#define ECP_ECR_SERVICE_INT_ON        0x04    // serviceIntr=1
#define ECP_ECR_SERVICE_INT_MASK      0xFB    // 1111 1011

// ECR nErrIntrEn bit 
#define ECP_ECR_ERR_BIT               0x10
#define ECP_ECR_ERR_BIT_ON            0x00

// ECR register FIFO pattern, forward direction
#define ECP_FIFOBITS_MASK    0x03    // 0000 0011
#define ECP_FIFO_EMPTY_MASK  0x01    // 0000 0001
#define ECP_FIFO_FULL_MASK   0x02    // 0000 0010
#define ECP_FIFO_EMPTY       0x01    // 0000 0001  empty pattern 01
#define ECP_FIFO_FULL        0x02    // 0000 0010  full pattern 10
#define ECP_HW_DETECT        0xFE    // 1111 1110

// ECP DCR register
#define ECP_DCR_DIRECTION_BIT_MASK    0xDF    // 1101 1111
#define ECP_DCR_DIRECTION_BIT_1       0x20    // 0010 0000
#define ECP_NACK_INT_OFF              0xEF    // 1110 1111
#define NINIT_LOW            0xFB    // 1111 1011  nInit Lo
#define NINIT_HIGH           0x04    // 0000 0100  nInit Hi
#define NAUTOFD_MASK         0xFD    // 1111 1101  nAutoFd Hi
#define NAUTOFD_LOW          0x02    // 0000 0010  nAutoFd Lo
#define NSTROBE_LOW          0x01    // 0000 0001  nStrobe Lo
#define NSTROBE_HIGH         0xFE    // 1111 1110  nStrobe Hi
#define CONTROL_CLEAR_MASK   0x40    // 0100 0000  clear except b6

// ECP forward direction
#define ECP_DCR_FOR_NEG      0x00    // 0000 0000  direction=0

// ECP Reverse direction
#define ECP_DCR_REV_NEG      0x32    // 0011 0010  direction=1, nAutoFd Lo
#define E_STATE40_MASK       0x28    // 0010 1000
#define E_STATE40_VALUE      0x08    // 0000 1000  PError Lo, nFault Hi
#define E_STATE49_MASK       0xE0    // 1110 0000
#define E_STATE49_VALUE      0xE0    // 1110 0000  Busy Lo, nAck Hi, PError Hi

// DSR register
#define NBUSY_BIT_LOW        0x80
#define NBUSY_BIT_HIGH       0x00
#define ECP_DSR_PERROR       0x40    // 0100 0000
#define ECP_DSR_PERROR_LOW   0x00    // 0000 0000
#define ECP_DSR_NFAULT       0x08    // 0000 1000
#define ECP_DSR_NFAULT_LOW   0x00    // 0000 0000
#define NACK_BIT_HIGH        0x40
#define NACK_BIT_LOW         0x00

// DMA requirements
#define DMA_ENABLE_BIT       0x08    // 0000 1000 used by ECR
#define DMA_TRANSFER_SETUP   0xFB    // 1111 1011 used by ECR
#define DMA_16_PAGES         0x10    // 16 pages  (16*4k)
#define DMA_8_PAGES          0x08    // 8 pages  (8*4k)
#define DMA_4_PAGES          0x04    // 4 pages  (4*4k)
#define DMA_1_PAGES          0x01    // 1 pages  (1*4k)
#define DMA_64K_ALIGN        0x0F    // 64K alignment
#define DMA_32K_ALIGN        0x07    // 32K alignment
#define DMA_16K_ALIGN        0x03    // 16K alignment
#define DMA_8K_ALIGN         0x01    // 8K alignment
#define DMA_4K_ALIGN         0x00    // 4K alignment
#define DMA_MAX_PAGE         0x0FF   // 64KB max DMA buffer
#define BYTES_PER_PAGE       0x0C    // 4096 bytes/page mask

#define ECP_DMA_WRITE        0x01
#define ECP_DMA_READ         0x02
#define ECP_WRITE            0x05
#define ECP_PIO_WRITE        0x04
#define ECP_PIO_READ         0x08
#define NIBBLE_READ          0x10
#define LPT_WRITE            0x20
#define READ_MASK            0x1a

// IRQ options in IRQ descriptor block
#define ECP_IRQ_OPTIONS      0       // not shareable

// DMA controller mode bit
#define ECP_DMA_READ_MODE    0x09    // read, demand, autoinc
#define ECP_DMA_WRITE_MODE   0x05    // write, demand, autoinc

#define ECP_MODE_MASK        0xE0    // 1110 0000
#define ECP_FIFO             0x40    // 0100 0000
#define ECP_ECP              0x60    // 0110 0000
#define ECP_PS2              0x20    // 0010 0000

// Interrupt mask
#define ISA_LEVEL            0x80
#define ISA_PULSE            0x00
#define INT_WAIT_SERVICE     0x01