mqhw2.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#define	FP_GPIO_MEDIUM		0x00001000UL	// GPIO0/1/2 drv strength - medium
#define	FP_GPIO_MEDIUM2		0x00002000UL	// GPIO0/1/2 drv strength - medium 2
#define	FP_GPIO_MIN			0x00003000UL	// GPIO0/1/2 drv strength - min
#define	FP_EN_MAX			0x00000000UL	// ENVDD/ENCTL/ENVEE - max (16mA)
#define	FP_EN_MEDIUM		0x00004000UL	// ENVDD/ENCTL/ENVEE - medium
#define	FP_EN_MEDIUM2		0x00008000UL	// ENVDD/ENCTL/ENVEE - medium 2
#define	FP_EN_MIN			0x0000c000UL	// ENVDD/ENCTL/ENVEE - min
#define GPO0_DATA_HIGH		0x00010000UL	// ENCTL is driven high
#define GPO1_DATA_HIGH		0x00020000UL	// ENVEE is driven high
#define GPO2_DATA_HIGH		0x00040000UL	// PWM0 is driven high
#define GPO3_DATA_HIGH		0x00080000UL	// PWM1 is driven high
#define GPO4_DATA_HIGH		0x00100000UL	// ENVDD is driven high

// FP_GPIO_CONTROL
//
#define GPIO0_IN			0x00000000UL	// General-purpose input
#define GPIO0_OUT			0x00000001UL	// General-purpose output
#define GPIO0_PLL1			0x00000002UL	// GPIO0 used to output PLL 1 clock
#define GPIO0_CRC_B			0x00000003UL	// GPIO0 used to output CRC Blue
#define GPIO1_IN			0x00000000UL	// General-purpose input
#define GPIO1_OUT			0x00000004UL	// General-purpose output
#define GPIO1_PLL2			0x00000008UL	// GPIO1 used to output PLL 2 clock
#define GPIO1_CRC_G			0x0000000cUL	// GPIO1 used to output CRC Green
#define GPIO2_IN			0x00000000UL	// General-purpose input
#define GPIO2_OUT			0x00000010UL	// General-purpose output
#define GPIO2_PLL3			0x00000020UL	// GPIO2 used to output PLL 3 clock
#define GPIO2_CRC_R			0x00000030UL	// GPIO2 used to output CRC Red
#define GPIO0_OUT_HIGH		0x00010000UL	// GOIO0 output data
#define GPIO1_OUT_HIGH		0x00020000UL	// GOIO1 output data
#define GPIO2_OUT_HIGH		0x00040000UL	// GOIO2 output data
#define GPIO0_IN_HIGH		0x01000000UL	// GOIO0 input data
#define GPIO1_IN_HIGH		0x02000000UL	// GOIO1 input data
#define GPIO2_IN_HIGH		0x04000000UL	// GOIO2 input data

// STN_CONTROL
//
#define FMOD_FRAMECLK		0x00000000UL	// FMOD generated using frame clock
#define FMOD_LINECLK		0x80000000UL	// FMOD generated using line clock

// PWM_CONTROL
//
#define PWM0_BY_PLL			0x00000000UL	// PWM 0 signal by PLL
#define PWM0_BY_BUS			0x00000001UL	// PWM 0 signal using bus clk
#define PWM0_BY_PMC			0x00000002UL	// PWM 0 signal by power mgt clock
#define PWM0_ALWAYS_ON		0x00000004UL	// PWM 0 signal always generated
#define PWM0_DC_MASK		0xffff00ffUL	// PWM 0 duty cycle mask
#define PWM0_MASK			0xffff0000UL	// PWM 0 mask
#define PWM1_BY_PLL			0x00000000UL	// PWM 1 signal by PLL
#define PWM1_BY_BUS			0x00010000UL	// PWM 1 signal using bus clk
#define PWM1_BY_PMC			0x00020000UL	// PWM 1 signal by power mgt clock
#define PWM1_ALWAYS_ON		0x00040000UL	// PWM 1 signal always generated
#define PWM1_DC_MASK		0x00ffffffUL	// PWM 0 duty cycle mask
#define PWM1_MASK			0x0000ffffUL	// PWM 1 mask

////////////////////////////////////////////////////////////////////////////////////
// PCI Power Management Interface Registers
//
#define PCI_VENDOR_DEVICE	0x00
#define PCI_CMD_STATUS		0x04
#define PCI_REV_CLASS		0x08
#define PCI_HEADER_TYPE		0x0c
#define PCI_SUB_ID			0x2c
#define PCI_ROM_BASE		0x30
#define PCI_CAP_PTR			0x34
#define PCI_INTERRUPT		0x3c
#define PCI_PM_REGISTER		0x40
#define PCI_PM_CNTL_STATUS	0x44

// POWER_STATE
//
#define POWER_STATE_MASK	0x00000003UL	// Device power state mask
#define ENTER_D0			0x00000000UL	// Enter D0 state
#define ENTER_D1			0x00000001UL	// Enter D1 state
#define ENTER_D2			0x00000002UL	// Enter D2 state
#define ENTER_D3			0x00000003UL	// Enter D3 state

////////////////////////////////////////////////////////////////////////////////////
// DC (Device Configuration Unit) Registers
//
#define DC_0				(0x00 * uBUSW)	// Device Configruation Register 0
#define DC_1				(0x01 * uBUSW)	// Device Configruation Register 1
#define	DC_SW_0				(0x02 * uBUSW)	// Software Register 0
#define	DC_SW_1				(0x03 * uBUSW)	// Software Register 1

// DC_0
#define	OSC_BYPASSED		0x00000001UL	// Oscillator bypassed, powered down
#define	OSC_ENABLE			0x00000002UL	// Oscillator control can be enabled
#define PLL1_BYPASSED		0x00000004UL	// PLL1 bypassed
#define PLL1_ENABLE			0x00000008UL	// PLL1 can be enabled
#define	PLL1_DIVBY1			0x00000000UL	// PLL1 P output divisor by 1
#define	PLL1_DIVBY2			0x00000010UL	// PLL1 P output divisor by 2
#define	PLL1_DIVBY4			0x00000020UL	// PLL1 P output divisor by 4
#define	PLL1_DIVBY8			0x00000030UL	// PLL1 P output divisor by 8
#define	PLL1_DIVBY16		0x00000040UL	// PLL1 P output divisor by 16
#define	PLL1_DIV_MASK		0x00000070UL	// PLL1 P output divisor mask
#define	CIF_DIVBY1			0x00000000UL	// CPU Interface clk divisor by 1
#define	CIF_DIVBY2			0x00000080UL	// CPU Interface clk divisor by 2
#define	STRONGARM_SYNC_F	0x00002000UL	// StrongARM bus intrf at fall edge
#define	SW_CHIP_RESET		0x00004000UL	// Software chip reset
#define	MEM_STANDBY_DISABLE	0x00008000UL	// Memory Power unit Standby disab.
#define	OSC_SHAPER_DISABLE	0x01000000UL	// Oscillator waveform shaper disab.
#define	FAST_POWER_DISABLE	0x02000000UL	// Fast Power Sequencing disable
#define	OSC_FREQ_SEL_0		0x00000000UL	// Osc frequency select range 0
#define	OSC_FREQ_SEL_1		0x04000000UL	// Osc frequency select range 1
#define	OSC_FREQ_SEL_2		0x08000000UL	// Osc frequency select range 2
#define	OSC_FREQ_SEL_3		0x0c000000UL	// Osc frequency select range 3

// DC_1
#define	BUS_MODE_MASK		0x0000003FUL	// Bus interface mode mask
#define	BUS_MODE_SH7709		0x00000001UL	// Bus interface mode - SH7709
#define	BUS_MODE_SH7750		0x00000002UL	// Bus interface mode - SH7750
#define	BUS_MODE_VR41xx		0x00000004UL	// Bus interface mode - VR4111/21
#define	BUS_MODE_SA1110		0x00000008UL	// Bus interface mode - SA1110
#define	BUS_MODE_TX3922		0x00000010UL	// Bus interface mode - TX3922
#define	BUS_MODE_PCI		0x00000020UL	// Bus interface mode - PCI

////////////////////////////////////////////////////////////////////////////////////
// PMU (Power Management Unit) Registers
//
#define PM_MISC				(0x00 * uBUSW)	// Power management misc control
#define D1_STATE			(0x01 * uBUSW)	// D1 state control
#define D2_STATE			(0x02 * uBUSW)	// D2 state control
#define PLL2_CONTROL		(0x06 * uBUSW)	// PLL2 programming
#define PLL3_CONTROL		(0x07 * uBUSW)	// PLL3 programming

// PM_MISC
//
#define PLL1_N_BIT5			0x00000001UL	// Bit 5 of PLL1 N parameter
#define PLL2_ENABLE			0x00000004UL	// PLL2 can be enabled
#define PLL3_ENABLE			0x00000008UL	// PLL3 can be enabled
#define FORCE_POWER_STATE	0x00000020UL	// For testing
#define GE_ENABLE			0x00000100UL	// Graphics engine can be enabled
#define GE_CLOCK_ON			0x00000200UL	// GE clock is always running
#define GE_PIPELINE_ON		0x00000400UL	// GE pipeline is always running
#define GE_BY_BUS			0x00000000UL	// GE driven by bus interface clock
#define GE_BY_PLL1			0x00000800UL	// GE driven by PLL1
#define GE_BY_PLL2			0x00001000UL	// GE driven by PLL2
#define GE_BY_PLL3			0x00001800UL	// GE driven by PLL3
#define GE_BY_MASK			0x00001800UL	// GE clock select mask
#define GE_CMDFIFO_RESET	0x00002000UL	// GE command FIFO is reset
#define GE_SRCFIFO_RESET	0x00004000UL	// GE CPU source FIFO is reset
#define	POWER_ON_IF_MIU_ON	0x00008000UL	// Pwr sequencing on when MIU enab.
#define D3_MEM_REFRESF		0x00010000UL	// Frame buffer is refreshed in D3
#define D4_MEM_REFRESF		0x00020000UL	// Frame buffer is refreshed in D4
#define PMCLK_4CYCLE		0x00000000UL	// Power sequencing interval
#define PMCLK_8CYCLE		0x00040000UL	// Power sequencing interval
#define PMCLK_16CYCLE		0x00080000UL	// Power sequencing interval
#define PMCLK_2048CYCLE		0x000c0000UL	// Power sequencing interval
#define FP_PMCLK_512		0x00000000UL	// Flat panel power seq interval
#define FP_PMCLK_1024		0x00100000UL	// Flat panel power seq interval
#define FP_PMCLK_2048		0x00200000UL	// Flat panel power seq interval
#define FP_PMCLK_128K		0x00300000UL	// Flat panel power seq interval
#define POWER_SEQ_ALL		0x00400000UL	// General power seq interval
#define PMU_TEST_MODE		0x008000UL		// PMU test mode
#define PM_POWER_MASK		0x03000000UL	// Power state mask
#define PM_D0_STATE			0x00000000UL	// Power state D0
#define PM_D1_STATE			0x01000000UL	// Power state D1
#define PM_D2_STATE			0x02000000UL	// Power state D2
#define PM_D3_STATE			0x03000000UL	// Power state D3
#define POWER_IN_PROGRESS	0x04000000UL	// Power sequencing active status

// D1_STATE and D2_STATE
//
#define DxOSC_ENABLE      	0x00000001UL	// Oscillator can be enabled in D1/2
#define DxPLL1_ENABLE     	0x00000002UL	// PLL1 can be enabled in D1/2
#define DxPLL2_ENABLE     	0x00000004UL	// PLL2 can be enabled in D1/2
#define DxPLL3_ENABLE     	0x00000008UL	// PLL3 can be enabled in D1/2
#define DxMIU_ENABLE      	0x00000010UL	// MIU can be enabled in D1/2
#define DxMEM_REFRESH		0x00000020UL	// Memory is refreshed in D1/2
#define DxGE_ENABLE    		0x00000040UL	// GE can be enabled in D1/2
#define DxCRT_ENABLE      	0x00000100UL	// CRT can be enabled in D1/2
#define DxFP_ENABLE       	0x00000200UL	// Flat panel can be enabled in D1/2
#define DxGC1_ENABLE      	0x00010000UL	// GC1 can be enabled in D1/2
#define DxW1_ENABLE       	0x00020000UL	// Window 1 can be enabled in D1/2
#define DxAW1_ENABLE      	0x00040000UL	// Alt window 1 enabled in D1/2
#define DxHC1_ENABLE      	0x00080000UL	// Cursor 1 enabled in D1/2
#define DxGC2_ENABLE      	0x01000000UL	// GC2 can be enabled in D1/2
#define DxW2_ENABLE       	0x02000000UL	// Window 2 can be enabled in D1/2
#define DxAW2_ENABLE      	0x04000000UL	// Alt window 2 enabled in D1/2
#define DxHC2_ENABLE      	0x08000000UL	// Cursor 2 enabled in D1/2

// PLL2_CONTROL
// PLL3_CONTROL
//
#define PLL_FROM_OSC      	0x00000000UL	// PLL2/3 ref clock from OSCCLK
#define PLL_FROM_PxCLK    	0x00000001UL	// PLL2/3 ref clock from P2CLK
#define PLL_BYPASSED      	0x00000002UL	// PLL2/3 is bypassed
#define PLL_DIVBY1 			0x00000000UL	// PLL2/3 P output divisor by 1
#define PLL_DIVBY2 			0x00000010UL	// PLL2/3 P output divisor by 2
#define PLL_DIVBY4 			0x00000020UL	// PLL2/3 P output divisor by 4
#define PLL_DIVBY8 			0x00000030UL	// PLL2/3 P output divisor by 8
#define PLL_DIVBY16			0x00000040UL	// PLL2/3 P output divisor by 16
#define PLL_DIV_MASK		0x00000070UL	// PLL2/3 P output divisor mask

////////////////////////////////////////////////////////////////////////////////////
// CPU Interface Registers
//
#define CPU_CONTROL			(0x00 * uBUSW)	// CPU control register
#define DRAW_STATUS			(0x01 * uBUSW)	// Drawing status register

// CPU_CONTROL
//
//#define SYNC_PALETTE1_2	0x00000001UL	// Enable color palette 1 & 2 write
#define SW_RESET			0x00000002UL	// Reset all modules except CIF
#define MIU_READ_REQ		0x00000004UL	// MIU read request
#define CLKRUN_ENABLE		0x00000008UL	// CLKRUN enabled. On Pwr-on, disab.
#define	FBCACHE_DISABLE		0x00000080UL	// Bit to disable frame buffer read cache

// DRAW_STATUS
//
#define CMD_FIFO_MASK		0x0000001fUL	// Command FIFO entries mask
#define SRC_FIFO_MASK		0x00001f00UL	// Source FIFO entry mask
#define GE_BUSY				0x00010000UL	// Any command in Comm FIFO
#define CMD_FIFO_FULL		0x00000000UL	// Cmd fifo full bit
#define CMD_FIFO_EMPTY		0x00000010UL	// Cmd fifo empty, 16x32 bits free
#define SRC_FIFO_FULL		0x00000000UL	// Src fifo full bit
#define SRC_FIFO_EMPTY		0x00000800UL	// Src fifo empty, 8x128 bits free

#define CMD_FIFO_CNT		16				// Command FIFO full entry
#if uBUSW == 4
#define	CMD_FIFO_MAX_INDEX	64
#elif uBUSW == 1
#define	CMD_FIFO_MAX_INDEX	16
#endif
#define SRC_FIFO_MAX_BYTES	128         	// max pixels in src fifo - 8bits
#define SRC_FIFO_MAX_WORDS	64          	// max pixels in src fifo - 16bits
#define SRC_FIFO_MAX_DWORDS	32				// max dwords in src fifo - 32bits

//////////////////////////////////////////////////////////////////////////////////////
// MIU (Memory Interface Unit) Registers
//
#define MIU_CONTROL1		(0x00 * uBUSW)	// Memory interface control 1
#define MIU_CONTROL2		(0x01 * uBUSW)	// Memory interface control 2
#define MIU_CONTROL3		(0x02 * uBUSW)	// Memory interface control 3
#define MIU_CONTROL4		(0x03 * uBUSW)	// Memory interface control 4
#define MIU_CONTROL5		(0x04 * uBUSW)	// Memory interface control 5

// MIU_CONTROL1
//
#define MIU_ENABLE			0x00000001UL	// Enable MIU
#define MIU_RESET_DISABLE	0x00000002UL	// MIU reset is disabled
#define DRAM_RESET_DISABLE	0x00000004UL	// DRAM reset is disabled

// MIU_CONTROL2
//
#define CLK_FROM_BUS		0x00000001UL	// Bus clock for mem clock source
#define CLK_FROM_PLL2		0x00000001UL	// PLL2 for mem clock source
#define MEM_REFRESH_ENABLE	0x00000002UL	// Mem refresh disab at pwr down mod
#define CPU_PB_ENABLE		0x00000004UL	// Page Break enab after CPU mem cyc
#define GC1_PB_ENABLE		0x00000008UL	// Page Break after GC1 mem cycles
#define GC2_PB_ENABLE		0x00000010UL	// Page Break after GC2 mem cycles
#define STN_R_PB_ENABLE		0x00000020UL	// Page Break after STN read mem cyc
#define STN_W_PB_ENABLE		0x00000040UL	// Page Break after STN wr. mem cyc
#define GE_PB_ENABLE		0x00000080UL	// Page Break after GE memory cycles
#define AUTO_REF_ENABLE		0x40000000UL	// Standby sig enab. when MIU active
#define	STANDBY_ENABLE		0x80000000UL	// Standby sig enab. when MIU active

// MIU_CONTROL3
//
#define DISPLAY_BURST2		0x00000000UL	// Burst size for disp mem refresh
#define DISPLAY_BURST4		0x00000001UL
#define DISPLAY_BURST6		0x00000002UL
#define DISPLAY_BURST8		0x00000003UL
#define STN_R_BURST2		0x00000000UL	// Burst size for STN read mem cycle
#define STN_R_BURST4		0x00000004UL
#define STN_R_BURST6		0x00000008UL
#define STN_R_BURST8		0x0000000cUL
#define STN_W_BURST2		0x00000000UL	// Burst size for STN write mem cyc
#define STN_W_BURST4		0x00000010UL
#define STN_W_BURST6		0x00000020UL
#define STN_W_BURST8		0x00000030UL
#define GE_RW_BURST2		0x00000000UL	// Burst size for GE r/w mem cycle
#define GE_RW_BURST4		0x00000040UL
#define GE_RW_BURST6		0x00000080UL
#define GE_RW_BURST8		0x000000c0UL
#define CPU_RW_BURST2		0x00000000UL	// Burst size for CPU r/w mem cycle
#define CPU_RW_BURST4		0x00000100UL
#define CPU_RW_BURST6		0x00000200UL
#define CPU_RW_BURST8		0x00000300UL

// MIU_CONTROL4
//
#define R_LATENCY_REQUEST	0x00000001UL	// Read Latency Request

// MIU_CONTROL5
//
#define	LATENCY_1			0x00000001UL	// EDRAM Latency 1
#define	LATENCY_2			0x00000005UL	// EDRAM Latency 2
#define	LATENCY_3			0x00000007UL	// EDRAM Latency 3
#define	DUMMY_IN_COMMANDS	0x00000008UL	// Dummy cycle insertion betw cmds
#define	DUMMY_IN_PRECHARGE	0x00000010UL	// Dummy cyc between precharge cyc 
#define DELAY_1ns			0x00000000UL	// Internal memory clock delay
#define	ACT_TO_CLOSE_3		0x00000100UL	// Bank activate to close - 3 mclk
#define	ACT_TO_CLOSE_4		0x00000200UL	// Bank activate to close - 4 mclk
#define	ACT_TO_CLOSE_5		0x00000300UL	// Bank activate to close - 5 mclk
#define	ACT_TO_COMMAND_2	0x00000000UL	// Bank activate to cmd r/w - 2 mclk
#define	ACT_TO_COMMAND_3	0x00000400UL	// Bank activate to cmd r/w - 3 mclk
#define	CLOSE_TO_ACT_2		0x00000000UL	// Bank close to activate - 2 mclk
#define	CLOSE_TO_ACT_3		0x00000800UL	// Bank close to activate - 3 mclk
#define	ROW_CYCLE_6			0x00000000UL	// Row Cycle time - 6 memory clock
#define	ROW_CYCLE_8			0x00001000UL	// Row Cycle time - 8 memory clock
#define	DELAY_R_CLOCK_0_0	0x00000000UL	// Delay for read clock - no delay
#define	DELAY_R_CLOCK_0_5	0x00010000UL	// Delay for read clock - 0.5ns
#define	DELAY_R_CLOCK_1_0	0x00020000UL	// Delay for read clock - 1.0ns
#define	DELAY_R_CLOCK_1_5	0x00030000UL	// Delay for read clock - 1.5ns
#define	DELAY_M_CLOCK_0_0	0x00000000UL	// Delay for memory clock - no delay
#define	DELAY_M_CLOCK_0_5	0x00020000UL	// Delay for memory clock - 0.5ns
#define	DELAY_M_CLOCK_1_0	0x00080000UL	// Delay for memory clock - 1.0ns
#define	DELAY_M_CLOCK_1_5	0x000c0000UL	// Delay for memory clock - 1.5ns

#endif __MQHW2_H__