📄 mqhw2.h
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#define BASE_ADDRESS2 (0x8b * uBUSW) // Base address register
#define TEST_RESULT_REG2 (0x1f * uBUSW) // Test result register
//#define SRC_IMAGE_DATA2 (0xa0 * uBUSW) // Source Data register
#define SRC_IMAGE_DATA2 (0x3000 * uBUSW) // Source Data register
#define COLOR_PATTERN2 (0xc0 * uBUSW) // Color pattern registers
#define MONO_PATTERN02 COLOR_PATTERN2 // Mono Pattern register 0
#define MONO_PATTERN12 (0xc1 * uBUSW) // Mono Pattern register 1
#define PAT_FG_COLOR2 (0xc2 * uBUSW) // Mono Pattern Foreground color reg
#define PAT_BG_COLOR2 (0xc3 * uBUSW) // Mono Pattern Background color reg
#define _FIRST_GE2 DRAW_CMD2
#define _LAST_GE2 (COLOR_PATTERN2 + (0x20 * uBUSW))
// DEST_STRIDE color depth
//
#define GE_8BPP 0x00000000 // 8BPP mode
#define GE_16BPP 0x40000000 // 16BPP mode
#define GE_24BPP 0x80000000 // 24BPP mode
#define GE_32BPP 0xC0000000 // 24BPP mode
// BASE_ADDRESS
//
#define GE_TEST_MODE_ENABLE 0x20000000 // Test mode enabled
#define GE_TEST_MASK 0xc0000000 // Test mode read path select
#define SEL_CLIP_LR 0x40000000 // Select clipping left/right
#define SEL_CLIP_TB 0x80000000 // Select clipping top/bottom
// Draw command register bits
//
#define DO_BITBLT 0x00000200
#define DO_AAFONT 0x00000300
#define DO_LINEDRAW 0x00000400
#define X_DIR 0x00000800 // Negative X direction
#define Y_DIR 0x00001000 // Negative Y direction
#define SRC_IS_MEMORY 0x00002000 // Source is in system memory
#define MONO_SRC 0x00004000 // Source is mono bitmap
#define MONO_PATTERN 0x00008000 // Pattern is monochrome
#define TRANS_COLOR 0x00010000 // Transparency is enabled
#define TRANS_NOT_EQUAL 0x00020000 // Polarity for color
#define TRANS_MONO 0x00040000 // Mono Transparency is enabled
#define TRANS_MONO_FG 0x00080000 // Polarity for mono
#define PACKED_MODE 0x00100000 // Memory xfer mode select
#define ALPHA_BYTE_MASK 0x00600000 // Alpha Byte mask for 32bpp
#define MONO_SOLID 0x00800000 // Solid Mono Pattern
#define SRC_NE_DEST_STRIDE 0x01000000 // Src Not Equal Dest Stride
#define ROP2_ENABLE 0x02000000 // Use Rop2 code
#define CLIP_ENABLE 0x04000000 // Clipping is enabled
#define AUTO_EXEC 0x08000000 // Auto execute at dest X/Y
#define VDE_GC2_ENABLE 0x10000000 // Enable falling edge check
#define VDE_GC1_ENABLE 0x20000000 // Enable falling edge check
#define COLOR_DEPTH_MASK 0xC0000000 // Color Depth mask
#define GE_8BPP 0x00000000 // 8BPP mode
#define GE_16BPP 0x40000000 // 16BPP mode
#define GE_24BPP 0x80000000 // 24BPP mode
#define geSID( data ) (REG32(GE_BASE,SRC_IMAGE_DATA) = data)
#define geSRCFIFO(id, data) (REG32(S1_BASE,id) = data)
/////////////////////////////////////////////////////////////////////////////
// Graphics Controller 1 Registers
//
#define GC1_CONTROL (0x00 * uBUSW) // Graphics Controll 1 Control Reg
#define GC1_CRT_CONTROL (0x01 * uBUSW) // CRT controll register
#define HD1_CONTROL (0x02 * uBUSW) // Horizontal Display 1 Control
#define VD1_CONTROL (0x03 * uBUSW) // Vertical Display 1 Control
#define HS1_CONTROL (0x04 * uBUSW) // Horizontal Sync 1 Control
#define VS1_CONTROL (0x05 * uBUSW) // Vertical Sync 1 Control
#define VD1_COUNT (0x07 * uBUSW) // Vertical Display 1 Count
#define HW1_CONTROL (0x08 * uBUSW) // Horizontal Window 1 Control
#define VW1_CONTROL (0x09 * uBUSW) // Vertical Window 1 Control
#define AHW1_CONTROL (0x0a * uBUSW) // Alt Horizontal Window 1 Control
#define AVW1_CONTROL (0x0b * uBUSW) // Alt Vertical Window 1 Control
#define IW1_START_ADDR (0x0c * uBUSW) // Image Window 1 Start Address
#define AIW1_START_ADDR (0x0d * uBUSW) // Alt Image Window 1 Start Address
#define IW1_STRIDE (0x0e * uBUSW) // (Alt) Image Window 1 Stride
#define IW1_LINE_SIZE (0x0f * uBUSW) // (Alt) Image Window 1 Line Size
// Hardware Cursor Registers
//
#define HW_CURSOR1_POS (0x10 * uBUSW) // Hardware cursor 1 position
#define HW_CURSOR1_ADDR (0x11 * uBUSW) // Start address and offset
#define HW_CURSOR1_FGCLR (0x12 * uBUSW) // Foreground color
#define HW_CURSOR1_BGCLR (0x13 * uBUSW) // Background color
// GC1_CONTROL/GC2_CONTROL register
//
#define GC_ENABLE 0x00000001UL // Controll 1/2 enabled
#define GC_DISABLE 0xfffffffeUL // Controll 1/2 disabled
#define HORZ_COUNT_RESET 0x00000002UL // Horizontal counter 1/2 reset
#define VERT_COUNT_RESET 0x00000004UL // Vertical counter 1/2 reset
#define IM_ENABLE 0x00000008UL // Image Window 1/2 Enable
#define IM_DISABLE 0xfffffff7UL // Image Window 1/2 Disable
#define GC_1BPP 0x00000000UL // GC1/2 color depth
#define GC_2BPP 0x00000010UL
#define GC_4BPP 0x00000020UL
#define GC_8BPP 0x00000030UL
#define GC_16BPP 0x00000040UL // with color palette enabled
#define GC_24BPP_NBP 0x00000050UL // with color palette enabled
#define GC_32BPP_ABGR 0x00000060UL // with color palette enabled
#define GC_32BPP_ARGB 0x00000070UL // with color palette enabled
#define GC_16BPP_BP 0x000000C0UL // with color palette bypassed
#define GC_24BPP_BP 0x000000D0UL // with color palette bypassed
#define GC_32BPP_ABGR_BP 0x000000E0UL // with color palette bypassed
#define GC_32BPP_ARGB_BP 0x000000F0UL // with color palette bypassed
#define GC_32BPP GC_32BPP_ARGB // Default 32bpp with ARGB
#define GC_24BPP GC_24BPP_NBP
#define HC_ENABLE 0x00000100UL // Hardware cursor enable
#define HC_DISABLE 0xfffffeffUL // And mask to disable HC
#define AIM_ENABLE 0x00000800UL // Alt Image Window 1/2 Enable
#define AGC_1BPP 0x00000000UL // Alt GC1/2 color depth
#define AGC_2BPP 0x00001000UL
#define AGC_4BPP 0x00002000UL
#define AGC_8BPP 0x00003000UL
#define AGC_16BPP 0x00004000UL
#define AGC_24BPP 0x00005000UL
#define AGC_32BPP_ABGR 0x00006000UL
#define AGC_32BPP_ARGB 0x00007000UL
#define AGC_16BPP_BP 0x0000C000UL
#define AGC_24BPP_BP 0x0000D000UL
#define AGC_32BPP_ABGR_BP 0x0000E000UL
#define AGC_32BPP_ARGB_BP 0x0000F000UL
#define AGC_32BPP AGC_32BPP_ARGB_BP // Default 32bpp with ARGB_BP
#define GxRCLK_BUSCLK 0x00000000UL // G1RCLK source is bus clock
#define GxRCLK_PLL1 0x00010000UL // G1RCLK source is PLL1
#define GxRCLK_PLL2 0x00020000UL // G1RCLK source is PLL2
#define GxRCLK_PLL3 0x00030000UL // G1RCLK source is PLL3
#define GxRCLK_PLL_MASK 0x00030000UL // G1RCLK source mask
#define GC_TEST_MODE0 0x00040000UL // Test mode 0 enabled
#define GC_TEST_MODE1 0x00080000UL // Test mode 1 enabled
#define FDx_1 0x00000000UL // FD1 = 1
#define FDx_15 0x00100000UL // FD1 = 1.5
#define FDx_25 0x00200000UL // FD1 = 2.5
#define FDx_35 0x00300000UL // FD1 = 3.5
#define FDx_45 0x00400000UL // FD1 = 4.5
#define FDx_55 0x00500000UL // FD1 = 5.5
#define FDx_65 0x00600000UL // FD1 = 6.5
// GC1_CRT_CONTROL register
//
#define CRT_ENABLE 0x00000001UL // CRT DAC enabled
#define CRT_DISABLE 0xfffffffeUL // CRT DAC disabled - and mask
#define CRT_BY_GC1 0x00000001UL // CRT DAC driven by GC1
#define CRT_BY_GC2 0x00000003UL // CRT DAC driven by GC2
#define CRT_BY_GCxMASK 0xfffffffcUL // Mask for CRT DAC
#define VSYNC_OUT_PMCLK 0x00000004UL // CRT VSYNC output PMCLK at PwrDn
#define HSYNC_OUT_PMCLK 0x00000008UL // CRT HSYNC output PMCLK at PwrDn
#define HSYNC_OUT_LOW 0x00000010UL // CRT HSYNC output pin low
#define HSYNC_OUT_HIGH 0x00000020UL // CRT HSYNC output pin high
#define VSYNC_OUT_LOW 0x00000040UL // CRT VSYNC output pin low
#define VSYNC_OUT_HIGH 0x00000080UL // CRT VSYNC output pin high
#define HSYNC_POLARITY_LOW 0x00000100UL // active low
#define VSYNC_POLARITY_LOW 0x00000200UL // active low
#define SYNC_PED_ENABLE 0x00000400UL // Sync pedestal enable
#define BLANK_PED_ENABLE 0x00000800UL // Blank pedestal enable
#define CSYNC_ENABLE 0x00001000UL // Composite Sync Enable
#define VREF_EXTERNAL 0x00002000UL // Select external VREF
#define MON_SENSE_ENABLE 0x00004000UL // CRT DAC monitor sense enable
#define CONST_OUT_ENABLE 0x00008000UL // Constant output enable
#define BLUE_NOT_LOADED 0x01000000UL // Blue DAC is not loaded
#define GREEN_NOT_LOADED 0x02000000UL // Green DAC is not loaded
#define RED_NOT_LOADED 0x04000000UL // Red DAC is not loaded
/////////////////////////////////////////////////////////////////////////////
// Graphics Controller 2 Registers
//
#define GC2_CONTROL (0x20 * uBUSW) // Graphics Controll 2 Control Reg
#define GC2_CRC_CONTROL (0x21 * uBUSW) // CRC Control
#define HD2_CONTROL (0x22 * uBUSW) // Horizontal Display 2 Control
#define VD2_CONTROL (0x23 * uBUSW) // Vertical Display 2 Control
#define HS2_CONTROL (0x24 * uBUSW) // Horizontal Sync 2 Control
#define VS2_CONTROL (0x25 * uBUSW) // Vertical Sync 2 Control
#define HW2_CONTROL (0x28 * uBUSW) // Horizontal Window 2 Control
#define VW2_CONTROL (0x29 * uBUSW) // Vertical Window 2 Control
#define AHW2_CONTROL (0x2a * uBUSW) // Alt Horizontal Window 2 Control
#define AVW2_CONTROL (0x2b * uBUSW) // Alt Vertical Window 2 Control
#define IW2_START_ADDR (0x2c * uBUSW) // Image Window 2 Start Address
#define AIW2_START_ADDR (0x2d * uBUSW) // Alt Image Window 2 Start Address
#define IW2_STRIDE (0x2e * uBUSW) // (Alt) Image Window 2 Stride
#define IW2_LINE_SIZE (0x2f * uBUSW) // (Alt) Image Window 2 Line Size
// Hardware Cursor Registers
//
#define HW_CURSOR2_POS (0x30 * uBUSW) // Hardware cursor 2 position
#define HW_CURSOR2_ADDR (0x31 * uBUSW) // Start address and offset
#define HW_CURSOR2_FGCLR (0x32 * uBUSW) // Foreground color
#define HW_CURSOR2_BGCLR (0x33 * uBUSW) // Background color
// GC2_CRC_CONTROL
//
#define CRC_ENABLE 0x00000001UL // Enable CRC logic
#define CRC_2_VSYNC 0x00000002UL // Wait for 2 vsync
#define CRC_READ_BLUE 0x00000000UL // Read CRC result for blue
#define CRC_READ_GREEN 0x00000004UL // Read CRC result for green
#define CRC_READ_RED 0x00000008UL // Read CRC result for red
#define CRC_RESULT_MASK 0x3fffff00UL // CRC result mask
/////////////////////////////////////////////////////////////////////////////
// Flat Panel Interface Registers
//
#define FP_CONTROL (0x00 * uBUSW) // Flat panel control
#define FP_PIN_CONTROL (0x01 * uBUSW) // Flat panel pin control
#define FP_GPO_CONTROL (0x02 * uBUSW) // FP General purpose output control
#define FP_GPIO_CONTROL (0x03 * uBUSW) // FP General purpose I/O control
#define STN_CONTROL (0x04 * uBUSW) // STN panel control
#define DSTN_FB_CONTROL (0x05 * uBUSW) // D-STN frame buffer control
#define PWM_CONTROL (0x0f * uBUSW) // PWM control
#define FRC_PATTERN (0x10 * uBUSW) // FRC pattern starting index
#define FRC_WEIGHT (0x30 * uBUSW) // FRC weight starting index
// FP_CONTROL
//
#define FPI_ENABLE 0x00000001UL // Trigger fp power up sequence
#define FPI_DISABLE 0xfffffffeUL // Trigger fp power down sequence
#define FPI_BY_GC1 0x00000001UL // FPI enabled and driven by GC1
#define FPI_BY_GC2 0x00000003UL // FPI enabled and driven by GC2
#define FPI_BY_GCx_MASK 0xfffffffcUL // mask
#define FP_TYPE_TFT 0x00000000UL // Flat panel type TFT
#define FP_TYPE_SSTN 0x00000004UL // Flat panel type S-STN
#define FP_TYPE_DSTN 0x00000008UL // Flat panel type D-STN
#define FP_TYPE_MASK 0x0000000cUL // Flat panel type mask
#define FP_COLOR 0x00000000UL // Color flat panel
#define FP_MONO 0x00000010UL // Mono flat panel
#define TFT_4BITS_MONO 0x00000000UL // Specify number of bits/pixel
#define TFT_12BITS_COLOR 0x00000000UL // Specify number of bits/pixel
#define SSTN_4BITS_MONOCLR 0x00000000UL // Specify number of bits/pixel
#define DSTN_8BITS_MONOCLR 0x00000000UL // Specify number of bits/pixel
#define TFT_6BITS_MONO 0x00000020UL // Specify number of bits/pixel
#define TFT_18BITS_COLOR 0x00000020UL // Specify number of bits/pixel
#define SSTN_8BITS_MONOCLR 0x00000020UL // Specify number of bits/pixel
#define DSTN_16BITS_MONOCLR 0x00000020UL // Specify number of bits/pixel
#define TFT_8BITS_MONO 0x00000040UL // Specify number of bits/pixel
#define TFT_24BITS_COLOR 0x00000040UL // Specify number of bits/pixel
#define SSTN_12BITS_COLOR 0x00000040UL // Specify number of bits/pixel
#define DSTN_24BITS_COLOR 0x00000040UL // Specify number of bits/pixel
#define SSTN_16BITS_MONOCLR 0x00000060UL // Specify number of bits/pixel
#define SSTN_24BITS_COLOR 0x00000080UL // Specify number of bits/pixel
#define DITHER_PATTERN_0 0x00000000UL // Dither pattern
#define DITHER_PATTERN_1 0x00000100UL // Dither pattern
#define DITHER_PATTERN_2 0x00000200UL // Dither pattern
#define DITHER_PATTERN_3 0x00000300UL // Dither pattern
#define DITHER_BASE_8BITS 0x00000000UL // No dithering
#define DITHER_BASE_2BITS 0x00002000UL // Number of bits to be dithered
#define DITHER_BASE_3BITS 0x00003000UL // Number of bits to be dithered
#define DITHER_BASE_4BITS 0x00004000UL // Number of bits to be dithered
#define DITHER_BASE_6BITS 0x00006000UL // Number of bits to be dithered
#define FRC_ALTWIN_DISABLE 0x00008000UL // Disable Dither/FRC if Alt enabled
#define FRC_2LEVEL 0x00000000UL // Disable FRC
#define FRC_4LEVEL 0x00010000UL // 4-level FRC
#define FRC_8LEVEL 0x00020000UL // 8-level FRC
#define FRC_16LEVEL 0x00030000UL // 16-level FRC
#define DITHER_PATTERN_ADJ1 0x00fc0000UL // Dither pattern adjust 1
#define DITHER_PATTERN_ADJ2 0x07000000UL // Dither pattern adjust 2
#define DITHER_PATTERN_ADJ3 0x08000000UL // Dither pattern adjust 3
#define TEST_MODE0_ENABLE 0x10000000UL // Enable test mode 0
#define TEST_MODE1_ENABLE 0x20000000UL // Enable test mode 1
#define TEST_MODE2_ENABLE 0x40000000UL // Enable test mode 2
#define TEST_MODE3_ENABLE 0x80000000UL // Enable test mode 3
// FP_PIN_CONTROL
//
#define FP_PIN_DISABLE 0x00000001UL // Disable flat panel pins
#define DATA_INV_ENABLE 0x00000002UL // TFT fp data inversion enabled
#define FP_DISP_ENABLE 0x00000004UL // FP Display enable control
#define FMOD_ENABLE 0x00000008UL // Flat panel AC mod enable
#define FD2_SCLK 0x00000010UL // STN output shift clock on FD2 pin
#define FSCLK_OUTPUT_ENABLE 0x00000020UL // FSCLK output enable
#define TFT_SCLK_SELECT 0x00000040UL // TFT shift clock select
#define SCLK_MASK 0x00000080UL // Shift clock mask
#define STN_LP_DISABLE 0x00000100UL // STN LP control
#define SCLK_DISABLE 0x00000200UL // STN shift clock control
#define STN_ExtraLP_ENABLE 0x00000400UL // STN extra LP control
#define FP_FD2_MAX 0x00000000UL // FD2 drive strength - max (16mA)
#define FP_FD2_MEDIUM 0x00001000UL // FD2 drive strength - medium
#define FP_FD2_MEDIUM2 0x00002000UL // FD2 drive strength - medium 2
#define FP_FD2_MIN 0x00003000UL // FD2 drive strength - min
#define FP_DATA_MAX 0x00000000UL // Data drive strength - max (16mA)
#define FP_DATA_MEDIUM 0x00004000UL // Data drive strength - medium
#define FP_DATA_MEDIUM2 0x00008000UL // Data drive strength - medium 2
#define FP_DATA_MIN 0x0000c000UL // Data drive strength - min
#define FD2_ACTIVE_L 0x00010000UL // Flat panel data bit 2 polarity
#define FD_ACTIVE_L 0x00020000UL // Flat panel data polarity
#define FDE_ACTIVE_L 0x00040000UL // Data enable polarity
#define FHSYNC_ACTIVE_L 0x00080000UL // Horz sync polarity
#define FVSYNC_ACTIVE_L 0x00100000UL // Vert sync polarity
#define FSCLK_ACTIVE_L 0x00200000UL // Shift clock polarity
#define FP_FSCLK_MAX 0x00000000UL // Sh clk drv strength - max (16mA)
#define FP_FSCLK_MEDIUM 0x00400000UL // Sh clk drv strength - medium
#define FP_FSCLK_MEDIUM2 0x00800000UL // Sh clk drv strength - medium 2
#define FP_FSCLK_MIN 0x00c00000UL // Sh clk drv strength - min
#define FSCLK_DELAY 0x07000000UL // Shift clock delay
// FP_GPO_CONTROL
//
#define ENCTL_AS_GPO0 0x00000001UL // ENCTL used as GPO 0
#define ENCTL_AS_OSC 0x00000002UL // ENCTL used as Oscillator clock
#define ENCTL_AS_PLL3 0x00000003UL // ENCTL used as PLL3 clock
#define ENVEE_AS_GPO1 0x00000004UL // ENVEE used as GPO 1
#define PWM0_AS_GPO2 0x00000010UL // PWM0 pin used as GPO 2
#define PWM1_AS_GPO3 0x00000040UL // PWM1 pin used as GPO 3
#define ENVDD_AS_GPO4 0x00000100UL // ENVDD pin used as GPO 4
#define FP_PWM_MAX 0x00000000UL // PWM0/1 drv strength - max (16mA)
#define FP_PWM_MEDIUM 0x00000400UL // PWM0/1 drv strength - medium
#define FP_PWM_MEDIUM2 0x00000800UL // PWM0/1 drv strength - medium 2
#define FP_PWM_MIN 0x00000c00UL // PWM0/1 drv strength - min
#define FP_GPIO_MAX 0x00000000UL // GPIO0/1/2 drv strength - max 16mA
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