mqhw2.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#ifndef __MQHW2_H__
#define __MQHW2_H__

//#ifdef MIPS
//#if defined(R4100) || defined(R4111) || defined(R4200) || defined(R4300)
//#define	MIPS_NEC
//#elif defined(R3000)
//#define	MIPS_TOS
//#endif
//#endif

//#ifdef x86
//#ifndef CEPC
//#define CEPC
//#endif
//#endif

//#ifdef SA1100
//#define	STRONG_ARM
////Use this devmap iff the physical address does not need shifting for
////VirtualCopy.  Certain customer's SA platform requires this devmap.
////#define  DEVMAP(x) if(1)
//#endif

//#ifdef EAGLE
//#define DEVMAP(x) if(0)
//#endif

//#ifdef HARRIER
//#define DEVMAP(x) if(0)
//#endif

// Default memory space macro for all platforms
#ifndef DEVMAP
#define  DEVMAP(x) x
#endif

// Chip Revision - moved to sources
//#define	REV_A
//#define	REV_B
//#define		REV_C
//#define		REV_0X

#ifdef	REV_0X
#define	ALWAYS_SET_DEST_STRIDE				//See comments in mqtables.h
#else
#define	MEM_REFRESH_PERIOD			64.0	//64ms dram refresh period
#endif

// Equates for chip debuggging and bug
//
#define NO_WAIT_PowerSeqOff

#define uBUSW					4			// processor bus width
#define MQ200_DEVICE			0x02004D51	// device=0x0100, vendor=0x0000
#define PM_ID_CAP				0x06210001	// Power management ID/capability
// Revision ID
#define MQ200_REV_0X					0x00
#define MQ200_REV_1A					0x01
#define MQ200_REV_1B1C				0x11
#define MQ200_REV_1D					0x10

// Generic typedef
//
#define SRC_IMAGE_DATA			(0x3000 * uBUSW)  // Source Data register for GE

#define CHECK_GE_NOTBUSY

#define geINIT( psurf ) 
#define	geTERMINATE()
#ifdef CHECK_GE_NOTBUSY
#define	geWAITNOTBUSY			WaitGENotBusy()
#else
#define	geWAITNOTBUSY
#endif	//CHECK_GE_NOTBUSY
#ifdef CHECK_SRCFIFO
#define	geWAITSRCFIFO( cnt )	WaitSrcFIFO( cnt )
#define	geWAITSRCFIFO1( cnt )	WaitSrcFIFO1( cnt )
#else
#define	geWAITSRCFIFO( cnt )
#define	geWAITSRCFIFO1( cnt )
#endif	//CHECK_SRCFIFO
#ifdef CHECK_CMDFIFO
#define	geWAITFULLCMDFIFO		WaitCmdFIFO( 16 )
//TMP MOVED BACK TO MQUTILS.BLT ==> BEN 5/28/99
//#ifdef ALWAYS_SET_DEST_STRIDE
//#define	geWAITCMDFIFO( cnt )	WaitCmdFIFO( (cnt + 1) )
//#else
#define	geWAITCMDFIFO( cnt )	WaitCmdFIFO( cnt )
//#endif	//ALWAYS_SET_DEST_STRIDE
#else	//CHECK_CMDFIFO
#define	geWAITFULLCMDFIFO
#define	geWAITCMDFIFO( cnt )
#endif	//CHECK_CMDFIFO

#define REG32(base, id)			(*((PULONG)(m_pMMIO+(base)+(id))))
#define REG32_PAL(base, idx)	(*((PULONG)(m_pMMIO+(base)+((idx)*uBUSW))))
#define REG32X_PAL(mmio, idx)	(*((PULONG)(mmio+((idx)*uBUSW))))

// Memory-mapped base address
//
//#ifdef	SHx
// #define FB_BASE				0x93800000L		// frame buffer - for sh3/4
//#elif defined( MIPS_NEC )
// #define FB_BASE				0xAA000000L		// frame buffer - for NEC MIPS
// #ifdef ENABLE_PCI
//  #define IOREGS_BASE			0xAF000000L		// IO register base - 4122
//  #define IOREGS_SIZE			0x00002000L		// IO register size
// #else
//  #define IOREGS_BASE			0xAB000000L		// IO register base - for NEC MIPS
//  #define IOREGS_SIZE			0x00001000L		// IO register size
// #endif // ENABLE_PCI
//#elif defined( MIPS_TOS )
//// #define FB_BASE				0x6F800000L		// frame buffer - for Toshiba MIPS
// #define FB_BASE				0x6D800000L		// frame buffer - for Toshiba MIPS
//#elif defined( STRONG_ARM )
// #define FB_BASE				0x4b800000L		// frame buffer - StrongARM (CS5)
//// #define FB_BASE			0x43800000L		// frame buffer - StrongARM (CS4)
//// #define FB_BASE			0x1b800000L		// frame buffer - StrongARM (CS3)
//#elif defined( CEPC )
// #define FB_BASE				0xff400000L		// frame buffer - for PCI on CEPC
//#elif defined( SC400 )
// #define FB_BASE				0xff400000L		// frame buffer - for PCI on AMD486
//#endif

//#ifdef CEPC
//#define MMIO_BASE			0xff800000L
//#elif defined( SC400 )
//#define MMIO_BASE			0xff800000L
//#else
//#define MMIO_BASE	  		(FB_BASE + 0x600000L)
//#endif
#define M_SIZE				0x00002000L 	// Size of each MQ module (8KB)

// MQ200 module offset
//
#define PM_BASE				0					// Power Management + Clk Gen
#define CC_BASE				(PM_BASE+M_SIZE)	// CPU interface
#define MM_BASE				(CC_BASE+M_SIZE)	// Memory Controller (m1/m2)
#define VI_BASE				(MM_BASE+M_SIZE)	// Video-in controller
#define IN_BASE				(VI_BASE+M_SIZE)	// Interrupt controller
#define GC_BASE				(IN_BASE+M_SIZE)	// Graphics Controller 1/2
#define GE_BASE				(GC_BASE+M_SIZE)	// Graphics engine
#define FP_BASE				(GE_BASE+M_SIZE)	// Flat panel interface
#define C1_BASE				(FP_BASE+M_SIZE)	// Color palette 1
#define C2_BASE				(C1_BASE+M_SIZE)	// Color palette 2
#define DC_BASE				(C2_BASE+M_SIZE)	// Device Configuration Space
#define PC_BASE				(DC_BASE+M_SIZE)	// PCI Configuration Header
#define PSF_BASE			(PC_BASE+M_SIZE)	// Primary Source FIFO Space
#define SSF_BASE			(PSF_BASE+M_SIZE)	// Secondary Source FIFO Space
#define LAST_BASE			(PSF_BASE+M_SIZE)	// First byte outside of MMIO

#define GE2_BASE			(GE_BASE+0x200 )	// Graphics engine (GE2)

#define MMIO_SIZE			(LAST_BASE - PM_BASE)	// memory-mapped size
#define FB_SIZE				0x200000L				// 2MB memory
#define LAST_ADDR          	0x200000L
#define LAST_KB				1024
#define GC_OFFSET			0x80

// Init and GE emulation are two different aminals
#define geREG(id, data)     (REG32(GE_BASE,id) = data)
#define geRREG( id )  		(REG32(GE_BASE,id))
//#define	gcREG(id, data)	(REG32(GC_BASE,id) = data)
#define	gcRREG( id )		(REG32(GC_BASE,id))

#define EmulInit()
#define DumpReg()
#define DumpPal()
#define DumpCursor()
#define gcREG(base,id,data)		(REG32(base,id)=data)
#define gcREAD(base,id)        	(REG32(base,id))
#define gc1REG(id,data)      	(REG32(GC_BASE,id)=data)
#define gc1READ(id)				(REG32(GC_BASE,id))
#define gc2REG(id,data)			(REG32(GC_BASE,id)=data)
#define gc2READ(id)        		(REG32(GC_BASE,id))
#define fpREG(id,data)			(REG32(FP_BASE,id)=data)
#define fpREAD(id)				(REG32(FP_BASE,id))
#define g1pREG(idx,data)		(REG32_PAL(C1_BASE,idx)=data)
#define g1pREAD(idx)			(REG32_PAL(C1_BASE,idx))
#define g2pREG(idx,data)		(REG32_PAL(C2_BASE,idx)=data)
#define g2pREAD(idx)			(REG32_PAL(C2_BASE,idx))
//#define palREG(mmio,idx,data)	(REG32X_PAL(mmio,idx)=data)
//#define palREAD(mmio,idx)   	(REG32X_PAL(mmio,idx))
#define palREG(idx,data)		(REG32_PAL(C1_BASE,idx)=data)
#define palREAD(idx)   			(REG32_PAL(C1_BASE,idx))
#define dcREG(id,data)			(REG32(DC_BASE,id)=data)
#define dcREAD(id)    			(REG32(DC_BASE,id))
#define pmuREG(id,data)			(REG32(PM_BASE,id)=data)
#define pmuREAD(id)    			(REG32(PM_BASE,id))
#define pciREG(id,data)			(REG32(PC_BASE,id)=data)
#define pciREAD(id)				(REG32(PC_BASE,id))
#define cpuREG(id,data)			(REG32(CC_BASE,id)=data)
#define cpuREAD(id)         	(REG32(CC_BASE,id))
#define miuREG(id,data)			(REG32(MM_BASE,id)=data)
#define miuREAD(id)         	(REG32(MM_BASE,id))
#define intREG(id,data)			(REG32(IN_BASE,id)=data)
#define intREAD(id)         	(REG32(IN_BASE,id))

////////////////////////////////////////////////////////////////////////////
// Interrupt Controller
//
#define INT_CONTROL_REG		(0x00 * uBUSW)	// Global interrupt control reg
#define INT_MASK_REG		(0x01 * uBUSW)	// Interrupt mask register
#define INT_STATUS_REG		(0x02 * uBUSW)	// Interrupt status register
#define INT_RAW_STATUS_REG	(0x03 * uBUSW)	// Interrupt pin raw status reg

// INT_CONTROL_REG - Global Interrupt Control Register
//
#define INT_ENABLE			0x00000001		// MQ200 interrupt to CPU enabled
#define INT_PORLARITY_HIGH	0x00000002		// Interrupt is active high
#define INT_GPIO1_0To1		0x00000004		// Interrupt as transition 0 to 1
#define INT_GPIO2_0To1		0x00000008		// Interrupt as transition 0 to 1
#define INT_GPIO3_0To1		0x00000010		// Interrupt as transition 0 to 1

// INT_MASK_REG -- Interrupt Mask Register
//
#define UM_GC1_VSE_R		0x00000001		// GC1 VSE - Rising edge
#define UM_GC1_VSE_F		0x00000002		// GC1 VSE - Falling edge
#define UM_GC1_VDE_R		0x00000004		// GC1 VDE - Rising edge
#define UM_GC1_VDE_F		0x00000008		// GC1 VDE - Falling edge
#define UM_GC2_VSE_R		0x00000010		// GC2 VSE - Rising edge
#define UM_GC2_VSE_F		0x00000020		// GC2 VSE - Falling edge
#define UM_GC2_VDE_R		0x00000040		// GC2 VDE - Rising edge
#define UM_GC2_VDE_F		0x00000080		// GC2 VDE - Falling edge
#define UM_CFIFO_HALF_EMPTY	0x00000100		// Command fifo half empty
#define UM_CFIFO_EMPTY		0x00000200		// Command fifo empty
#define UM_SFIFO_HALF_EMPTY	0x00000400		// Source fifo half empty
#define UM_SFIFO_EMPTY		0x00000800		// Source fifo empty
#define UM_GE_IDLE			0x00001000		// GE is idle
#define UM_GPIO_1			0x00002000		// GPIO pin 1
#define UM_GPIO_2			0x00004000		// GPIO pin 2
#define UM_GPIO_3			0x00008000		// GPIO pin 3

// INT_STATUS_REG -- Interrupt Status Register
//
#define ST_GC1_VSE_R		0x00000001		// GC1 VSE - Rising edge
#define ST_GC1_VSE_F		0x00000002		// GC1 VSE - Falling edge
#define ST_GC1_VDE_R		0x00000004		// GC1 VDE - Rising edge
#define ST_GC1_VDE_F		0x00000008		// GC1 VDE - Falling edge
#define ST_GC2_VSE_R		0x00000010		// GC2 VSE - Rising edge
#define ST_GC2_VSE_F		0x00000020		// GC2 VSE - Falling edge
#define ST_GC2_VDE_R		0x00000040		// GC2 VDE - Rising edge
#define ST_GC2_VDE_F		0x00000080		// GC2 VDE - Falling edge
#define ST_CFIFO_HALF_EMPTY	0x00000100		// Command fifo half empty
#define ST_CFIFO_EMPTY		0x00000200		// Command fifo empty
#define ST_SFIFO_HALF_EMPTY	0x00000400		// Source fifo half empty
#define ST_SFIFO_EMPTY		0x00000800		// Source fifo empty
#define ST_GE_IDLE			0x00001000		// GE is idle
#define ST_GPIO_1			0x00002000		// GPIO pin 1
#define ST_GPIO_2			0x00004000		// GPIO pin 2
#define ST_GPIO_3			0x00008000		// GPIO pin 3

// INT_RAW_STATUA_REG -- Interrupt Pin Raw Status Register
//
#define GC1_VSE				0x00000001		// GC1 - VSE
#define GC1_VDE				0x00000004		// GC1 - VDE
#define GC2_VSE				0x00000010		// GC2 - VSE
#define GC2_VDE				0x00000040		// GC2 - VDE
#define INT_GE_BUSY			0x00000100		// GE busy
#define SFIFO_EMPTY			0x00000200		// Source fifo empty
#define SFIFO_HEMPTY		0x00000400		// Source fifo half empty
#define CFIFO_EMPTY			0x00000800		// Command fifo empty
#define CFIFO_HEMPTY		0x00001000		// Command fifo half empty
#define GPIO_PIN_1			0x00002000		// GPIO pin 1
#define GPIO_PIN_2			0x00004000		// GPIO pin 2
#define GPIO_PIN_3			0x00008000		// GPIO pin 3

// 2D Engine registers - GE1 (0x00 - 0x7F)
//
#define DRAW_CMD			(0x00 * uBUSW)	// Drawing command register
#define WIDTH_HEIGHT		(0x01 * uBUSW)	// Width/height register
#define	LINE_DRAW			WIDTH_HEIGHT	// Bresenham Line Draw register
#define DEST_XY				(0x02 * uBUSW)  // Destination X/Y register
#define LINE_MAJOR_X		DEST_XY         // Bresenham Line Start X/Y register
#define PAT_OFFSET			DEST_XY         // Pattern Offset register
#define SRC_XY				(0x03 * uBUSW)  // Source X/Y register
#define LINE_MINOR_Y		SRC_XY          // Bresenham Line Delta register
#define COLOR_COMPARE		(0x04 * uBUSW)  // Color compare register
#define CLIP_LeftT			(0x05 * uBUSW)  // Clip Left/Top register
#define CLIP_RightB			(0x06 * uBUSW)  // Clip Right/Bottom register
#define FG_COLOR			(0x07 * uBUSW)  // Foreground color for Mono src reg
#define BG_COLOR			(0x08 * uBUSW)  // Background color for Mono src reg
#define SRC_STRIDE_OFFSET	(0x09 * uBUSW)  // Source Stride & Offset Register
#define DEST_STRIDE			(0x0a * uBUSW)  // Base address register
#define BASE_ADDRESS		(0x0b * uBUSW)  // Base address register
#define TEST_RESULT_REG		(0x1f * uBUSW)  // Test result register
#define COLOR_PATTERN		(0x40 * uBUSW)  // Color pattern registers
#define MONO_PATTERN0		COLOR_PATTERN   // Mono Pattern register 0
#define MONO_PATTERN1		(0x41 * uBUSW)  // Mono Pattern register 1
#define PAT_FG_COLOR		(0x42 * uBUSW)  // Mono Pattern Foreground color reg
#define PAT_BG_COLOR		(0x43 * uBUSW)  // Mono Pattern Background color reg
#define	_FIRST_GE			DRAW_CMD
#define	_LAST_GE			(COLOR_PATTERN + (0x20 * uBUSW))

// 2D Engine registers - GE2 (0x80 to 0xFF)
//
#define DRAW_CMD2			(0x80 * uBUSW)  // Drawing command register
#define WIDTH_HEIGHT2		(0x81 * uBUSW)  // Width/height register
#define	LINE_DRAW2			WIDTH_HEIGHT2   // Bresenham Line Draw register
#define DEST_XY2			(0x82 * uBUSW)  // Destination X/Y register
#define LINE_MAJOR_X2		DEST_XY2		// Bresenham Line Start X/Y register
#define PAT_OFFSET2			DEST_XY2        // Pattern Offset register
#define SRC_XY2				(0x83 * uBUSW)  // Source X/Y register
#define LINE_MINOR_Y2		SRC_XY2			// Bresenham Line Delta register
#define COLOR_COMPARE2		(0x84 * uBUSW)  // Color compare register
#define CLIP_LeftT2			(0x85 * uBUSW)  // Clip Left/Top register
#define CLIP_RightB2		(0x86 * uBUSW)  // Clip Right/Bottom register
#define FG_COLOR2			(0x87 * uBUSW)  // Foreground color for Mono src reg
#define BG_COLOR2			(0x88 * uBUSW)  // Background color for Mono src reg
#define SRC_STRIDE_OFFSET2	(0x89 * uBUSW)  // Source Stride & Offset Register
#define DEST_STRIDE2		(0x8a * uBUSW)  // Base address register