config.cpp

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

		SetupCRTTiming( xc, yc, fc );

		//Make display visible
		HW_Enable_LCD( GC2 );
		HW_Enable_CRT( GC1 );			//GC1 defined in mqext.ccp
	}
	return;
}

//This routine retrieves proper timing parameters from pre-defined table
//- used for both LCD and CRT
PMQ_TIMING_PARAM
MQGC::GetMQTiming(USHORT x, USHORT y, USHORT freq)
{
	for (int i=0; i < MAX_MQTIMING; i++)
	{
		if ( MQTimingParam[i].usResoX == x
			&& MQTimingParam[i].usResoY == y
			&& MQTimingParam[i].usFreq == freq )
			return ( (PMQ_TIMING_PARAM)&MQTimingParam[i] );
	}
	return ((PMQ_TIMING_PARAM)&MQTimingParam[0]);		//not found - return first table entry
}

//This routine program CRT timing parameters
ULONG
MQGC::GetBPPBits(void)
{
	ULONG	ulTemp;

	//Set up color depth for both Window and Alt Window properly
	switch( m_ulBPP )
	{
		case  8UL: ulTemp = GC_8BPP;	break;
		case 16UL: ulTemp = GC_16BPP_BP;	break;
		case 24UL: ulTemp = GC_24BPP_BP;	break;
		case 32UL: ulTemp = GC_32BPP_ARGB_BP;	break;
		case  4UL: ulTemp = GC_4BPP;	break;
		case  2UL: ulTemp = GC_2BPP;	break;
		case  1UL: ulTemp = GC_1BPP;	break;
		default: ulTemp = 0; break;
	}

	switch( OemInfo.usAWBPP )
	{
		case  1: ulTemp |= AGC_1BPP;	break;
		case  2: ulTemp |= AGC_2BPP;	break;
		case  4: ulTemp |= AGC_4BPP;	break;
		case  8: ulTemp |= AGC_8BPP;	break;
		case 16: ulTemp |= AGC_16BPP_BP;	break;
		case 24: ulTemp |= AGC_24BPP_BP;	break;
		case 32: ulTemp |= AGC_32BPP_ARGB_BP;	break;
		default: ulTemp |= 0; break;
	}

	return (ulTemp);
}

//This routine program LCD timing parameters - in general, LCD timing
//remains unchanged.
//
//flag:
//	==0	do not program hori/vert display and sync control
//	!=0	program hori/vert display and sync control registers too
void
MQGC::SetupLCDTiming(USHORT x, USHORT y, USHORT freq, USHORT flag)
{
	USHORT	usTemp;
	ULONG	ulTemp;
	ULONG	ulHW_ControlLCD, ulVW_ControlLCD;
	ULONG	ulAHW, ulAVW, ulAIWStartAddr;

	// Reprogram MIU registers if necessary ...
	//
	if (!(m_nMQFlag & FULL_SETMODE))
		PatchMIU();

	//Set up LCD Window-related registers
	//- Center it if desktop window is smaller than panel size
	//- You could actually treat LCD as fixed-freq device
	//
	
	if (x < m_pFPControl->usHoriSize)
	{
		usTemp = (m_pFPControl->usHoriSize - x) / 2;
		ulHW_ControlLCD = ((x - 1) << 16) | usTemp;
	}
	else
		ulHW_ControlLCD = (m_pFPControl->usHoriSize - 1) << 16;

	if (y < m_pFPControl->usVertSize)
	{
		usTemp = (m_pFPControl->usVertSize - y) / 2;
		ulVW_ControlLCD = ((y - 1) << 16) | usTemp;
	}
	else
  		ulVW_ControlLCD = (m_pFPControl->usVertSize - 1) << 16;

	// Alternate window size and start address
	//
	ulAHW = (ULONG)(OemInfo.usAWX - 1) << 16 | (x - OemInfo.usAWX) >> 1;
	ulAVW = (ULONG)(OemInfo.usAWY - 1) << 16 | (y - OemInfo.usAWY) >> 1;
	ulAIWStartAddr = (ADDRESS)(m_pPrimarySurface->OffsetInVideoMemory()) +
							(ulAVW & 0x0000ffff) * m_ulScreenStride +
							(ulAHW & 0x0000ffff) * m_nBytesPerPixel;
	
	ULONG ulGCBase = GC_BASE;
  	if (flag & LCD_BY_GC2)
	{
		ulGCBase += GC_OFFSET;
		CursorData.usGC2VPL = 0;
		CursorData.usGC2VPT = 0;
		CursorData.usGC2VPR = x - 1;
		CursorData.usGC2VPB = y - 1;
		CursorData.usGC2VPL2 = 0;
		CursorData.usGC2VPT2 = 0;
		CursorData.usGC2VPR2 = x - 1;
		CursorData.usGC2VPB2 = y - 1;
		gc2REG(IW2_START_ADDR, m_nIW2StartAddr);
	}
	else
	{
		CursorData.usGC1VPL = 0;
		CursorData.usGC1VPT = 0;
		CursorData.usGC1VPR = x - 1;
		CursorData.usGC1VPB = y - 1;
		CursorData.usGC1VPL2 = 0;
		CursorData.usGC1VPT2 = 0;
		CursorData.usGC1VPR2 = x - 1;
		CursorData.usGC1VPB2 = y - 1;
		gc1REG(IW1_START_ADDR, m_nIW1StartAddr);
	}

	gcREG(ulGCBase, AHW1_CONTROL,		ulAHW);
	gcREG(ulGCBase, AVW1_CONTROL,		ulAVW);
	gcREG(ulGCBase, AIW1_START_ADDR,	ulAIWStartAddr);

	gcREG(ulGCBase, HW1_CONTROL,		ulHW_ControlLCD);
	gcREG(ulGCBase, VW1_CONTROL,		ulVW_ControlLCD);

	if (flag & RELOAD_TIMING)
	{
		gcREG(ulGCBase, HD1_CONTROL, m_pFPControl->ulHD);
		gcREG(ulGCBase, VD1_CONTROL, m_pFPControl->ulVD);
		gcREG(ulGCBase, HS1_CONTROL, m_pFPControl->ulHS);
		gcREG(ulGCBase, VS1_CONTROL, m_pFPControl->ulVS);

#ifdef	FLEX_PLL
		ULONG	ulPMMisc, ulGCReg;
		SetMQPLL( m_pFPControl->fPLLFreq, PLL_GC2, &ulPMMisc, &ulGCReg );

		ulTemp = pmuREAD(PM_MISC) | ulPMMisc;		//get current setting
		if (!(m_pFPControl->ulFPControl & FP_TYPE_MASK))
			ulTemp |= FP_PMCLK_1024; // for STN
  		pmuREG(PM_MISC, ulTemp);

		//Enable GC2 after correct timing in place
		if (!(flag & NO_SETUP_GC1))
		{
			ulTemp = GetBPPBits()
						| (m_pFPControl->ulClockData
						| IM_ENABLE
						| ulGCReg);			//GxRCLK_PLLx is OEM-dependent!
			gcREG(ulGCBase,GC1_CONTROL, ulTemp);
		}
#else	//FLEX_PLL
		//Use PLL3 to drive GC2
		ULONG		ulClockData;
		SetMQPLL( m_pFPControl->fPLLFreq, PLL_GC2, &ulPLL3, &ulClockData );
		fPLL3 = m_pFPControl->fPLLFreq;
		pmuREG(PLL3_CONTROL, ulPLL3);
		ulTemp = pmuREAD(PM_MISC) | PLL3_ENABLE;	//get current setting
		if (!(m_pFPControl->ulFPControl & FP_TYPE_MASK))
			ulTemp |= FP_PMCLK_1024; // for STN
	#if 1	//def MIPS_NEC
		//HSU - begin Patch to allow PLL1/MIU Clk to lower if allowable
		if ( bMIUClkLow
			&& (x <= 800) && (y <= 600) && (m_ulBPP <= 16)
			&& fDC0 > 50.0F )
		{
			ULONG	ulPLL1;
			fDC0 = 50.0F;
			SetMQPLL( fDC0, PLL_MIU, &ulPLL1, NULL );
			ulPLL1 = ulPLL1 | ( dcREAD(DC_0) & 0xFF00000F );
			dcREG(DC_0, ulPLL1);
			ulMIU2 &= ~0x3FFF000UL;
			ulMIU2 |= (( COMPUTE_REFRESH_PERIOD( fDC0 ) << 12) & 0x03FFF000UL);
			miuREG(MIU_CONTROL2, ulMIU2);
		}
		else if ( fDC0 < 83.0F )
		{
			ULONG	ulPLL1;
			fDC0 = 83.0F;
			SetMQPLL( fDC0, PLL_MIU, &ulPLL1, NULL );
			ulPLL1 = ulPLL1 | ( dcREAD(DC_0) & 0xFF00000F );
			dcREG(DC_0, ulPLL1);
			ulMIU2 &= ~0x3FFF000UL;
			ulMIU2 |= (( COMPUTE_REFRESH_PERIOD( fDC0 ) << 12) & 0x03FFF000UL);
			miuREG(MIU_CONTROL2, ulMIU2);
		}
		//HSU - end
	#endif
		DetermineGE( &ulTemp );
  		pmuREG(PM_MISC, ulTemp);

		//Enable GC2 after correct timing in place
		if (!(flag & NO_SETUP_GC1))
		{
			ulTemp = GetBPPBits()
					  | (ulClockData
						| IM_ENABLE
						| GxRCLK_PLL3);		//GxRCLK_PLL3 is OEM-dependent!
			gcREG(ulGCBase,GC1_CONTROL, ulTemp);
		}
#endif	//FLEX_PLL
	}
}

void MQGC::PatchMIU(void)
{
	HKEY		hRegKey;
	ULONG		ulData, ulStatus, ulValType, ulValLen;

	// Get required MIU data from Registry ...
	ulStatus = DrvEnableDriverOpen( &hRegKey );
	REG_ASSIGN( ulMIU3, tcMIU3, ulData, 0xFFFFFFFF);
	RegCloseKey(hRegKey);

	if (ulMIU4 != 0xFFFFFFFF)
		miuREG(MIU_CONTROL3, ulMIU3);

	return;
}

#define VGA_X			640
#define VGA_Y			480
void
MQGC::SetupCRTTiming(USHORT x, USHORT y, USHORT freq, WORD GC)
{
	ULONG		ulTemp, ulPMMisc;
	ULONG		ulHW_ControlCRT, ulVW_ControlCRT;

	// Reprogram MIU registers if necessary ...
	//
	if (!(m_nMQFlag & FULL_SETMODE))
		PatchMIU();

	// If desktop size is smaller than VGA size, use VGA timing but center
	// active display to desktop size
	if (y < VGA_Y)
	{
		ulTemp = (VGA_Y - y) / 2;
		ulVW_ControlCRT = ((y - 1) << 16) | ulTemp;
		y = VGA_Y;	// make it VGA timing
	}
	else
		ulVW_ControlCRT = (y - 1) << 16;

	if (x < VGA_X)
	{
		ulTemp = (VGA_X - x) / 2;
		ulHW_ControlCRT = ((x - 1) << 16) | ulTemp;
		x = VGA_X;	// make it VGA timing
	}
	else
		ulHW_ControlCRT = (x - 1) << 16;

	m_pCRTTiming = GetMQTiming(x, y, freq);

	//ulHW_ControlCRT = x << 16;
	//ulVW_ControlCRT = y << 16;

	if(GC == GC1)
	{
		CursorData.usGC1VPL = 0;
		CursorData.usGC1VPT = 0;
		CursorData.usGC1VPR = x - 1;
		CursorData.usGC1VPB = y - 1;
		CursorData.usGC1VPL2 = 0;
		CursorData.usGC1VPT2 = 0;
		CursorData.usGC1VPR2 = x - 1;
		CursorData.usGC1VPB2 = y - 1;
		gc1REG(IW1_START_ADDR, m_nIW1StartAddr);

		gc1REG(HW1_CONTROL, ulHW_ControlCRT);
		gc1REG(VW1_CONTROL, ulVW_ControlCRT);

		gc1REG(HD1_CONTROL, m_pCRTTiming->ulHD);
		gc1REG(VD1_CONTROL, m_pCRTTiming->ulVD);
		gc1REG(HS1_CONTROL, m_pCRTTiming->ulHS);
		gc1REG(VS1_CONTROL, m_pCRTTiming->ulVS);
	}
	else
	{
		CursorData.usGC2VPL = 0;
		CursorData.usGC2VPT = 0;
		CursorData.usGC2VPR = x - 1;
		CursorData.usGC2VPB = y - 1;
		CursorData.usGC2VPL2 = 0;
		CursorData.usGC2VPT2 = 0;
		CursorData.usGC2VPR2 = x - 1;
		CursorData.usGC2VPB2 = y - 1;
		//gc2REG(IW2_START_ADDR, m_nIW2StartAddr);
		
		gc2REG(HW2_CONTROL, ulHW_ControlCRT);
		gc2REG(VW2_CONTROL, ulVW_ControlCRT);

		gc2REG(HD2_CONTROL, m_pCRTTiming->ulHD);
		gc2REG(VD2_CONTROL, m_pCRTTiming->ulVD);
		gc2REG(HS2_CONTROL, m_pCRTTiming->ulHS);
		gc2REG(VS2_CONTROL, m_pCRTTiming->ulVS);
	}

#ifdef FLEX_PLL
	ulTemp = GetBPPBits()
			| IM_ENABLE
			//| HC_ENABLE
			;

	ULONG	ulGCCtrl;
	SetMQPLL( m_pCRTTiming->fPLLFreq, PLL_GC1, &ulPMMisc, &ulGCCtrl );
#else	//FLEX_PLL
	ULONG	ulClockData = FDx_1 | (1UL << 24);
	ulTemp = GetBPPBits()
			| IM_ENABLE
			//| HC_ENABLE
			//| m_pCRTTiming->ulClockData
			;

	if (m_nMQFlag & USE_2GCs)
	{
		if (m_pCRTTiming->fPLLFreq != m_pFPControl->fPLLFreq)
		{
			// Use PLL2 to drive GC1
			SetMQPLL( m_pCRTTiming->fPLLFreq, PLL_GC1, &ulPLL2, &ulClockData );
			fPLL2 = m_pCRTTiming->fPLLFreq;
			pmuREG(PLL2_CONTROL, ulPLL2);
			ulPMMisc = pmuREAD(PM_MISC) | PLL2_ENABLE;	// get current setting
		#if 1	//def MIPS_NEC
			//HSU - begin
			if ( fDC0 < 83.0F )
			{
				ULONG	ulPLL1;
				fDC0 = 83.0F;
				SetMQPLL( fDC0, PLL_MIU, &ulPLL1, NULL );
				ulPLL1 = ulPLL1 | ( dcREAD(DC_0) & 0xFF00000F );
				dcREG(DC_0, ulPLL1);
				ulMIU2 &= ~0x3FFF000UL;
				ulMIU2 |= ((COMPUTE_REFRESH_PERIOD(fDC0) << 12) & 0x03FFF000UL);
				miuREG(MIU_CONTROL2, ulMIU2);
			}
			//HSU - end
		#endif
			DetermineGE( &ulPMMisc );
  			pmuREG(PM_MISC, ulPMMisc);
			ulTemp |= GxRCLK_PLL2;
		}
		else
		{
			ulTemp |= GxRCLK_PLL3;
		}
	}
	else
	{
		// Use PLL2 to drive GC1
		SetMQPLL( m_pCRTTiming->fPLLFreq, PLL_GC1, &ulPLL2, &ulClockData );
		fPLL2 = m_pCRTTiming->fPLLFreq;
		pmuREG(PLL2_CONTROL, ulPLL2 );
		ulPMMisc = pmuREAD(PM_MISC) | PLL2_ENABLE;	// get current setting
	#if 1	//def MIPS_NEC
			//HSU - begin
			if ( fDC0 < 83.0F )
			{
				ULONG	ulPLL1;
				fDC0 = 83.0F;
				SetMQPLL( fDC0, PLL_MIU, &ulPLL1, NULL );
				ulPLL1 = ulPLL1 | ( dcREAD(DC_0) & 0xFF00000F );
				dcREG(DC_0, ulPLL1);
				ulMIU2 &= ~0x3FFF000UL;
				ulMIU2 |= ((COMPUTE_REFRESH_PERIOD(fDC0) << 12) & 0x03FFF000UL);
				miuREG(MIU_CONTROL2, ulMIU2);
			}
			//HSU - end
	#endif
		DetermineGE( &ulPMMisc );
  		pmuREG(PM_MISC, ulPMMisc);
		gc1REG(GC1_CRT_CONTROL, CRT_BY_GC1|BLANK_PED_ENABLE|MON_SENSE_ENABLE); // how about the rest bits?
		ulTemp |= GxRCLK_PLL2;
	}
	ulTemp |= ulClockData;

#endif	//FLEX_PLL


	//Set up GC1_CONTROL register - but GC1 remains disabled
	if ( GC == GC1 )
		gc1REG(GC1_CONTROL, ulTemp);
	else
		gc2REG(GC2_CONTROL, ulTemp);
}

SCODE
MQGC::GetModeInfo(
		GPEMode *pMode,
		int modeNo )
{
	if ( modeNo<0 || modeNo >= NumModes() )
		return E_INVALIDARG;

	*pMode = MQVideoMode[modeNo].gpeMode;
	
	DEBUGMSG (GPE_ZONE_INIT, (TEXT("GetModeInfo:X=%x\r\n"),pMode->width));
	DEBUGMSG (GPE_ZONE_INIT, (TEXT("GetModeInfo:Y=%x\r\n"),pMode->height));
	DEBUGMSG (GPE_ZONE_INIT, (TEXT("GetModeInfo:BPP=%x\r\n"),pMode->Bpp));
	DEBUGMSG (GPE_ZONE_INIT, (TEXT("GetModeInfo:freq=%x\r\n"),pMode->frequency));
	return S_OK;
}

int
MQGC::NumModes()
{
	return 1;		//1 all the time
}

void
MQGC::GetPhysicalVideoMemory(
	unsigned long *pPhysicalMemoryBase,
	unsigned long *pVideoMemorySize )
{
	*pPhysicalMemoryBase = m_nLAWPhysical;
	*pVideoMemorySize = m_nVideoMemorySize;
}

void
MQGC::GetVirtualVideoMemory(
	unsigned long *pVirtualMemoryBase,
	unsigned long *pVideoMemorySize )
{
	*pVirtualMemoryBase = (unsigned long)m_pLAW;
	*pVideoMemorySize = m_nVideoMemorySize;
}