panels.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 10 : DSTN 16Bit SVGA Color Panel - 60Hz
	// - Hitachi 10.0" SX25S001
	// - Hitachi 12.1" SX25S003
	// - Sanyo LM-FC53-22NTK
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1056-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		840 | (968L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00f50a30,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
	#else
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00e90830,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

#if 1
	0x0C1B4128
#else
		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0C840000		
#endif
        ,
		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 11 : DSTN 24Bit XGA Color Panel - 60Hz
	// - Hitachi 12.1" SX25S003
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00eb0c20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#else
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00fd0b20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_24BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 12 : DSTN 16Bit XGA Color Panel - 60Hz
	// - Hitachi 12.1" SX25S003
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00eb0c20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#else
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00fd0b20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 13 : TFT 18Bit XGA - 60Hz
	// - Hitachi 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00eb0c20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#else
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00fd0b20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| FHSYNC_ACTIVE_L
		| FVSYNC_ACTIVE_L
		//| FP_SCLK_16mA
		//| FP_DATA_16mA 
		,

		// STN panel control
		0x00bd0001
	},

	// Type 14 : TFT 24Bit XGA - 60Hz
	// - Hitachi 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		1024,
		768,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00eb0c20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#else
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),			// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00fd0b20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_24BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| FHSYNC_ACTIVE_L
		| FVSYNC_ACTIVE_L
		//| FP_SCLK_16mA
		//| FP_DATA_16mA 
		,

		// STN panel control
		0x00bd0001
	},
	
	// Type 15 : TFT 18 Bit SVGA - 60Hz (Similar to type 4)
	// - NEC 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1056-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		840 | (968L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00f50a30,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
	#else
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00e90830,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		0x03000020
		//FSCLK_OUTPUT_ENABLE
		//| FHSYNC_ACTIVE_L
		//| FVSYNC_ACTIVE_L
		//| FP_FSCLK_MAX
		//| FP_FD2_MAX
		//| FP_DATA_MAX
		,

		// STN panel control
		0x00bd0001
	},
	
	// Type 16 : SSTN VGA 8Bit Color - 90Hz
	// - Sharp LM8M64 SSTN 640x240 8-bit color interface
	//
	{	// Flat panel control
		640,
		240,

		// Flat panel timing
	#ifdef RCLK_14_318
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((240L-1) << 16),		// VD Total + VD End
		664 | (704L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#else
		(793-2) | (640L << 16),			// HD Total + HD End
		(262-1) | ((240L-1) << 16),		// VD Total + VD End
		647 | (704L << 16),				// HS Start + HS End
		245 | (246L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		25.175F,							// PLLx frequency
	#endif

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_8BITS_MONOCLR
		| DITHER_PATTERN_1
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
	}
};

// Flat panel FRC weight/pattern registers
//
FRC_CONTROL_STRUC FRCControlData[] =
{
	{
		// FRC Pattern Data - 6B84 (for DSTN)
		0x97A4C5F8,
		0x61E3DB02,
		0xD3E081BC,
		0x25A79F46,
		0x5B680934,
		0xAD2F17CE,
		0x1F2C4D70,
		0xE96B538A,
		0x0E3D5C61,
		0xF87A429B,
		0x4A791825,
		0xBC3E06DF,
		0xC2F190AD,
		0x34B68E57,
		0x86B5D4E9,
		0x70F2CA13,
		0xF1C2A39E,
		0x0785BD64,
		0xB586E7DA,
		0x43C1F920,
		0x3D0E6F52,
		0xCB4971A8,
		0x794A2B16,
		0x8F0D35EC,
		0x685B3A07,
		0x9E1C24FD,
		0x2C1F7E43,
		0xDA5860B9,
		0xA497F6CB,
		0x52D0E831,
		0xE0D3B28F,
		0x1694AC75,

		// FRC weight data
		0x80800000,
		0x88888420,
		0x94a49248,
		0xaaaaaa54,
		0x6b5b55ab,
		0x77776db7,
		0x7f7f7bdf,
		0xffff7fff
	},

	// FRC Pattern Data - 2FCA (for SSTN)
	{
		0x97A4C5F8,
		0x61E3DB02,
		0xD3E081BC,
		0x25A79F46,
		0x4A791825,
		0xBC3E06DF,
		0x0E3D5C61,
		0xF87A429B,
		0xF1C2A39E,
		0x0785BD64,
		0xB586E7DA,
		0x43C1F920,
		0x2C1F7E43,
		0xDA5860B9,
		0x685B3A07,
		0x9E1C24FD,
		0xE0D3B28F,
		0x1694AC75,
		0xA497F6CB,
		0x52D0E831,
		0x3D0E6F52,
		0xCB4971A8,
		0x794A2B16,
		0x8F0D35EC,
		0x86B5D4E9,
		0x70F2CA13,
		0xC2F190AD,
		0x34B68E57,
		0x5B680934,
		0xAD2F17CE,
		0x1F2C4D70,
		0xE96B538A,

		// FRC weight data
		0x80800000,
		0x88888420,
		0x94a49248,
		0xaaaaaa54,
		0x6b5b55ab,
		0x77776db7,
		0x7f7f7bdf,
		0xffff7fff
	}
};

#endif __PANELS_H__