panels.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#ifndef __PANELS_H__
#define __PANELS_H__

// Flat panel control register
//
FP_CONTROL_STRUC FPControlData[] =
{

	// Type OEM panel :
	//
	{	// Flat panel control
		0,
		0,

		// Flat panel timing
		0,						// HD Total + HD End
		0,						// VD Total + VD End
		0,						// HS Start + HS End
		0,						// VS Start + VS End
		0.0F,					// PLLx frequency

		// Flat panel Control
		0,

		// Flat panel pin control
		0,

		// STN panel control
		0x0
	},
	// Type 1 : SSTN VGA 8Bit Color - 72Hz
	// - Sanyo SSTN 640x480 8-bit color interface
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),	// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#else
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),	// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#endif

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_8BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
	},

	// Type 2 : DSTN 16 Bit VGA Color - 72Hz
	// - Hitachi 8.2" SX21V001
	// - Sanyo 10.4" LM-CJ53-22NTK
	// - Sharp 10.4" LM64C35P
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#else
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 3 : TFT 18 Bit VGA - 60Hz
	// - NEC 10.4" NL6448AC33-24
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00e00740,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
	#else
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00a30930,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		,

		// STN panel control
		0x00bd0001
	},

	// Type 4 : TFT 18 Bit SVGA - 60Hz
	// - Hitachi 12.1" 800x600 TX31D24VC1CAA
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1056-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		840 | (968L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00f50a30,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
	#else
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),			// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00e90830,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_TFT
		| FP_COLOR
		| TFT_18BITS_COLOR
		| DITHER_PATTERN_3
		| DITHER_BASE_6BITS 
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		//| FHSYNC_ACTIVE_L
		//| FVSYNC_ACTIVE_L
		//| FP_FSCLK_MAX
		//| FP_FD2_MAX
		//| FP_DATA_MAX
		,

		// STN panel control
		0x00bd0001
	},

	// Type 5 : DSTN 16Bit SVGA Color Panel - 72Hz
	// - Hitachi 10.0" SX25S001
	// - Hitachi 12.1" SX25S003
	//
	{	// Flat panel control
		800,
		600,

		// Flat panel timing
	#ifdef RCLK_14_318
		(1038-2) | (800L << 16),		// HD Total + HD End
		(666-1) | ((600L-1) << 16),			// VD Total + VD End
		854 | (974L << 16),				// HS Start + HS End
		637 | (643L << 16),				// VS Start + VS End
		//0x00fa0830,					// PLLx multiplier and control
		50.0F,							// PLLx frequency
	#else
		(1040-2) | (800L << 16),		// HD Total + HD End
		(666-1) | ((600L-1) << 16),			// VD Total + VD End
		856 | (976L << 16),				// HS Start + HS End
		637 | (643L << 16),				// VS Start + VS End
		//0x00b20a20,					// PLLx multiplier and control
		50.0F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 6 : DSTN 8 Bit VGA Color - 72Hz
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(832-2) | (640L << 16),       	// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#else
		(832-2) | (640L << 16),       	// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_8BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0001
	},

	// Type 7 : SSTN VGA 16Bit Color - 72Hz
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(832-2) | (640L << 16),       	// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#else
		(832-2) | (640L << 16),       	// HD Total + HD End
		(520-1) | ((480L-1) << 16),			// VD Total + VD End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		//| FP_SCLK_16mA
		//| FP_FD0_16mA
		//| FP_DATA_16mA
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
	},

	// Type 8 : SSTN VGA 8Bit Color - 60Hz
	// - Sanyo SSTN 640x480 8-bit color interface
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00e00740,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
	#else
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00a30930,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_SSTN
		| FP_COLOR
		| SSTN_8BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x00400000
		,

		// Flat panel pin control
		FSCLK_OUTPUT_ENABLE
		| SCLK_MASK
		| FDE_ACTIVE_L	
		,

		// STN panel control
		0x00bd0000
	},

	// Type 9 : DSTN 16 Bit VGA Color - 60Hz
	// - Hitachi 8.2" SX21V001
	// - Sanyo 10.4" LM-CJ53-22NTK
	// - Sharp 10.4" LM64C35P
	//
	{	// Flat panel control
		640,
		480,

		// Flat panel timing
	#ifdef RCLK_14_318
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00e00740,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
	#else
		(800-2) | (640L << 16),       	// HD Total + HD End
		(525-1) | ((480L-1) << 16),			// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00a30930,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
	#endif // (RCLK_14_318)

		// Flat panel Control
		FP_TYPE_DSTN
		| FP_COLOR
		| DSTN_16BITS_MONOCLR
		| DITHER_PATTERN_3
		| DITHER_BASE_4BITS
		| FRC_16LEVEL
		| 0x0c840000
		,