devmap.cpp

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#include "precomp.h"
#include <windows.h>
#include <stdarg.h>
#include "mqhw2.h"
#include "mqgc.h"

//////////////////////////////////////////////////////////////////////////////////////

#pragma optimize("",off)

#define	DRIVER_REGISTRY_STRING	(L"Drivers\\Display\\MQ200PCI")

#define MQDEV  0x0200
#define MQVEN	0x4d51

extern ULONG	ulFBBase;
#if	0	
#ifdef ENABLE_PCI

// Include additional header files specific to PCI
#include <nkintr.h>
#include <oalintr.h>
#include <types.h>
#include <ceddk.h>

// Define HAL function call
#ifndef MIPS_NEC
//#define HalGetBusData(type,bus,slot,buffer,length) \
//			PCIGetBusDataByOffset(bus,slot,buffer,0,length)
//#define HalSetBusData(type,bus,slot,buffer,length) \
//			PCISetBusDataByOffset(bus,slot,buffer,0,length)
#else
#define HalGetBusData(type,bus,slot,buffer,length) \
			HalGetBusDataByOffset(type,bus,slot,buffer,0,length)

#define HalSetBusData(type,bus,slot,buffer,length) \
			HalSetBusDataByOffset(type,bus,slot,buffer,0,length)
#endif

/*============================================================================
 *  Function: DebugPrintf
 *  Description: print message on console
 *===========================================================================*/
VOID
DebugPrintf(PTCHAR pszFormat, ...)
{
    static  TCHAR   szString[256];
    static  UCHAR   szAnsiString[256];
    static  int     hConsole;
    va_list         args;

    va_start(args, pszFormat);

    wvsprintf(szString, pszFormat, args);

#ifdef USE_CONSOLE
    if (hConsole == 0)
    {
        hConsole = U_ropen(TEXT("con"), _O_WRONLY);
    }

    if (hConsole != 0 && hConsole != -1)
    {
        int     nLength;
        BOOL    bDefaultUsed;

        nLength = WideCharToMultiByte(
            CP_ACP, WC_COMPOSITECHECK | WC_DEFAULTCHAR,
            szString, _tcslen(szString),(LPSTR)szAnsiString, sizeof(szAnsiString),
            "?", &bDefaultUsed);

        U_rwrite(hConsole, szAnsiString, nLength);
    }
    else
#endif /* USE_CONSOLE */
    {
        OutputDebugString(szString);
    }

    va_end(args);
}

/*============================================================================
 *  Function: DeviceType
 *  Description: Determine PCI device type
 *===========================================================================*/
PTCHAR
DeviceType(UCHAR ucBaseClass, UCHAR ucSubClass, UCHAR ucProgIf)
{
    static  struct  
    {
        ULONG   ulClass;
        PTCHAR  pszDescription;
    }   ClassNames[] = 
    {
        { 0x000000, TEXT("Pre 2.0 Non VGA device") },
        { 0x000101, TEXT("Pre 2.0 VGA device") },
        { 0x010000, TEXT("SCSI Controller") },
        { 0x010100, TEXT("IDE Controller") },
        { 0x010180, TEXT("Busmaster IDE Controller") },
        { 0x010200, TEXT("Floppy Controller") },
        { 0x010300, TEXT("IPI Controller") },
        { 0x010400, TEXT("RAID Controller") },
        { 0x018000, TEXT("Other Mass Storage Device") },
        { 0x020000, TEXT("Ethernet Network Controller") },
        { 0x020100, TEXT("Token Ring Network Controller") },
        { 0x020200, TEXT("FDDI Network Controller") },
        { 0x020300, TEXT("ATM Network Controller") },
        { 0x028000, TEXT("Other Network Controller") },
        { 0x030000, TEXT("VGA Compatible Display Adapter") },
        { 0x030001, TEXT("8514 Compatible Display Adapter") },
        { 0x030100, TEXT("XGA Compatible Display Adapter") },
        { 0x038000, TEXT("Other Display Adapter") },
        { 0x040000, TEXT("Video Multimedia Device") },
        { 0x040100, TEXT("Audio Multimedia Device") },
        { 0x048000, TEXT("Other Multimedia Device") },
        { 0x050000, TEXT("RAM Memory Controller") },
        { 0x050100, TEXT("Flash Memory Controller") },
        { 0x058000, TEXT("Other Memory Controller") },
        { 0x060000, TEXT("Host / PCI Bridge") },
        { 0x060100, TEXT("PCI / ISA Bridge") },
        { 0x060200, TEXT("PCI / EISA Bridge") },
        { 0x060300, TEXT("PCI / MCA Bridge") },
        { 0x060400, TEXT("PCI / PCI Bridge") },
        { 0x060500, TEXT("PCI / PCMCIA Bridge") },
        { 0x060600, TEXT("NuBus Bridge") },
        { 0x060700, TEXT("CardBus Bridge") },
        { 0x068000, TEXT("Other Bridge") },
        { 0x070000, TEXT("8250 Compatible Communications Device") },
        { 0x070001, TEXT("16450 Compatible Communications Device") },
        { 0x070002, TEXT("16550 Compatible Communications Device") },
        { 0x070100, TEXT("Parallel Port") },
        { 0x070101, TEXT("Bidirectional Parallel Port") },
        { 0x070102, TEXT("ECP 1.X Parallel Port") },
        { 0x078000, TEXT("Other Communications Device") },
        { 0x0C0000, TEXT("Firewire (IEEE 1394) Bus Controller") },
        { 0x0C0100, TEXT("ACCESS.bus Controller") },
        { 0x0C0200, TEXT("SSA Controller") },
        { 0x0C0300, TEXT("UHCI USB Bus Controller") },
        { 0x0C0301, TEXT("OHCI USB Bus Controller") },
    };
#define NUMBER_CLASS_NAMES  (sizeof(ClassNames) / sizeof(ClassNames[0]))

    ULONG   ulClassKey;
    int     i;

    ulClassKey = (ucBaseClass << 16) | (ucSubClass << 8) | ucProgIf;

    for (i = 0; i < NUMBER_CLASS_NAMES; i++)
    {
        if (ClassNames[i].ulClass == ulClassKey)
        {
            return ClassNames[i].pszDescription;
        }
    }

    return TEXT("Unknown Device Type");
}

/*============================================================================
 *  Function: DumpPciConfig
 *  Description: Print PCI ConfigSpace
 *===========================================================================*/
VOID
DumpPciConfig(int Bus, int Device, int Function, PPCI_COMMON_CONFIG pPciConfig)
{
    DebugPrintf(
        TEXT("\r\nBus/Device/Function = %d/%d/%d, %s\r\n"),
        Bus, Device, Function,
        DeviceType(pPciConfig->BaseClass, pPciConfig->SubClass, pPciConfig->ProgIf));

    DebugPrintf(
        TEXT("  VendorID = 0x%4.4X, DeviceID = 0x%4.4X, Command = 0x%4.4X, Status = 0x%4.4X\r\n"),
        pPciConfig->VendorID, pPciConfig->DeviceID, pPciConfig->Command, pPciConfig->Status);

    DebugPrintf(
        TEXT("  RevisionID = 0x%2.2X, ProgIf = 0x%2.2X, SubClass = 0x%2.2X, BaseClass = 0x%2.2X\r\n"),
        pPciConfig->RevisionID, pPciConfig->ProgIf, pPciConfig->SubClass, pPciConfig->BaseClass);

    DebugPrintf(
        TEXT("  CacheLineSize = 0x%2.2X, LatencyTimer = 0x%2.2X, HeaderType = 0x%2.2X, BIST = 0x%2.2X\r\n"),
        pPciConfig->CacheLineSize, pPciConfig->LatencyTimer, pPciConfig->HeaderType, pPciConfig->BIST);

    switch (pPciConfig->HeaderType & 0x7F)
    {
    case 0:
        DebugPrintf(TEXT("  BaseAddresses:\r\n"));

        DebugPrintf(
            TEXT("    0x%8.8X  0x%8.8X  0x%8.8X  0x%8.8X  0x%8.8X  0x%8.8X\r\n"),
            pPciConfig->u.type0.BaseAddresses[0], pPciConfig->u.type0.BaseAddresses[1],
            pPciConfig->u.type0.BaseAddresses[2], pPciConfig->u.type0.BaseAddresses[3],
            pPciConfig->u.type0.BaseAddresses[4], pPciConfig->u.type0.BaseAddresses[5]);

        DebugPrintf(
            TEXT("  CIS = 0x%8.8X, SubVendorID = 0x%4.4X, SubSystemID = 0x%4.4X\r\n"),
            pPciConfig->u.type0.CIS, pPciConfig->u.type0.SubVendorID,
            pPciConfig->u.type0.SubSystemID);

        DebugPrintf(
            TEXT("  ROMBaseAddress = 0x%8.8X\r\n"),
            pPciConfig->u.type0.ROMBaseAddress);

        DebugPrintf(
            TEXT("  InterruptLine = 0x%2.2X, InterruptPin = 0x%2.2X, MinGrant = 0x%2.2X, MaxLatency = 0x%2.2X\r\n"),
            pPciConfig->u.type0.InterruptLine, pPciConfig->u.type0.InterruptPin,
            pPciConfig->u.type0.MinimumGrant, pPciConfig->u.type0.MaximumLatency);
        break;

    case 1:
        DebugPrintf(
            TEXT("  BaseAddresses = 0x%8.8X 0x%8.8X\r\n"),
            pPciConfig->u.type1.BaseAddresses[0], pPciConfig->u.type1.BaseAddresses[1]);

        DebugPrintf(
            TEXT("  PrimaryBusNumber = %d, SecondaryBusNumber = %d\r\n"),
            pPciConfig->u.type1.PrimaryBusNumber, pPciConfig->u.type1.SecondaryBusNumber);

        DebugPrintf(
            TEXT("  SubordinateBusNumber = %d, SecondaryLatencyTimer = %d\r\n"),
            pPciConfig->u.type1.SubordinateBusNumber, pPciConfig->u.type1.SecondaryLatencyTimer);

        DebugPrintf(
            TEXT("  IOBase = 0x%2.2X, IOLimit = 0x%2.2X, SecondaryStatus = 0x%4.4X\r\n"),
            pPciConfig->u.type1.IOBase, pPciConfig->u.type1.IOLimit,
            pPciConfig->u.type1.SecondaryStatus);

        DebugPrintf(
            TEXT("  MemoryBase = 0x%4.4X, MemoryLimit = 0x%4.4X\r\n"),
            pPciConfig->u.type1.MemoryBase, pPciConfig->u.type1.MemoryLimit);

        DebugPrintf(
            TEXT("  PrefetchableMemoryBase = 0x%4.4X, PrefetchableMemoryLimit = 0x%4.4X\r\n"),
            pPciConfig->u.type1.PrefetchableMemoryBase, pPciConfig->u.type1.PrefetchableMemoryLimit);

        DebugPrintf(
            TEXT("  PrefetchableMemoryBaseUpper32 = 0x%8.8X\r\n"),
            pPciConfig->u.type1.PrefetchableMemoryBaseUpper32);

        DebugPrintf(
            TEXT("  PrefetchableMemoryLimitUpper32 = 0x%8.8X\r\n"),
            pPciConfig->u.type1.PrefetchableMemoryLimitUpper32);

        DebugPrintf(
            TEXT("  IOBaseUpper = 0x%4.4X, IOLimitUpper = 0x%4.4X\r\n"),
            pPciConfig->u.type1.IOBaseUpper, pPciConfig->u.type1.IOLimitUpper);

        DebugPrintf(
            TEXT("  Reserved2 = 0x%8.8X, ExpansionROMBase = 0x%8.8X\r\n"),
            pPciConfig->u.type1.Reserved2, pPciConfig->u.type1.ExpansionROMBase);