modes.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#ifndef __MODES_H__
#define __MODES_H__


// LCD/CRT timing parameters for each resolution
//
MQ_TIMING_PARAM MQTimingParam[] = 
{
#ifdef RCLK_14_318
	{	// 640 x 480 60Hz (25.175 MHz)
		640,480,60,							// X/Y/Freq
		(800-2) | (640L << 16),			// HD Total + HD End
		(525-1) | ((480L-1) << 16),	// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00e00740,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{	// 640 x 480 72Hz (31.5 MHz)
		640,480,72,							// X/Y/Freq
		(832-2) | (640L << 16),			// HD Total + HD End
		(520-1) | ((480L-1) << 16),	// VD Total + VD End
		664 | (704L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 640 x 480 75Hz (31.5 MHz)
		640,480,75,							// X/Y/Freq
		(840-2) | (640L << 16),      	// HD Total + HD End
		(500-1) | ((480L-1) << 16),	// VD Total + VD End
		656 | (720L << 16),				// HS Start + HS End
		481 | (484L << 16),				// VS Start + VS End
		//0x00af0930,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 640 x 480 85Hz (36 MHz)
		640,480,85,							// X/Y/Freq
		(832-2) | (640L << 16),       // HD Total + HD End
		(509-1) | ((480L-1) << 16),	// VD Total + VD End
		696 | (752L << 16),				// HS Start + HS End
		481 | (484L << 16),				// VS Start + VS End
		//0x00b40830,					// PLLx multiplier and control
		36.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 800 x 600 60Hz (40 MHz)
		800,600,60,							// X/Y/Freq
		(1056-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),	// VD Total + VD End
		840 | (968L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00f50a30,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 800 x 600 72Hz 50 MHz)
		800,600,72,							// X/Y/Freq
		(1038-2) | (800L << 16),		// HD Total + HD End
		(666-1) | ((600L-1) << 16),	// VD Total + VD End
		854 | (974L << 16),				// HS Start + HS End
		637 | (643L << 16),				// VS Start + VS End
		//0x00fa0830,					// PLLx multiplier and control
		50.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 800 x 600 75Hz (49.5 MHz)
		800,600,75,							// X/Y/Freq
		(1056-2) | (800L << 16),		// HD Total + HD End
		(625-1) | ((600L-1) << 16),	// VD Total + VD End
		816 | (896L << 16),				// HS Start + HS End
		601 | (604L << 16),				// VS Start + VS End
		//0x00a50b20,					// PLLx multiplier and control
		49.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 800 x 600 85Hz (56.25 MHz)
		800,600,85,							// X/Y/Freq
		(1048-2) | (800L << 16),		// HD Total + HD End
		(631-1) | ((600L-1) << 16),	// VD Total + VD End
		832 | (896L << 16),				// HS Start + HS End
		601 | (604L << 16),				// VS Start + VS End
		//0x00db0d20,					// PLLx multiplier and control
		56.25F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 1024 x 768 60Hz (65 MHz)
		1024,768,60,						// X/Y/Freq
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00eb0c20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},			

	{  // 1024 x 768 70Hz (75 MHz)
		1024,768,70,						// X/Y/Freq
		(1326-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1046 | (1182L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00fa0b20,					// PLLx multiplier and control
		75.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 1024 x 768 75Hz (78.750 MHz)
		1024,768,75,						// X/Y/Freq
		(1312-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1040 | (1136L << 16),			// HS Start + HS End
		769 | (772L << 16),				// VS Start + VS End
		//0x00f10a20,					// PLLx multiplier and control
		78.75F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 1024 x 768 85Hz (94.5 MHz)
		1024,768,85,						// X/Y/Freq
		(1376-2) | (1024L << 16),		// HD Total + HD End
		(808-1) | ((768L-1) << 16),	// VD Total + VD End
		1072 | (1168L << 16),			// HS Start + HS End
		769 | (772L << 16),				// VS Start + VS End
		//0x00830910,					// PLLx multiplier and control
		94.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	}

 #if 0 // No support for 95MHz or more
	{  // 1152 x 864 75Hz (108 MHz)
		1152,864,75,						// X/Y/Freq
		(1600-2) | (1152L << 16),		// HD Total + HD End
		(900-1) | ((864L-1) << 16),	// VD Total + VD End
		1216 | (1344L << 16),			// HS Start + HS End
		865 | (868L << 16),				// VS Start + VS End
		//0x00b40b10,					// PLLx multiplier and control
		108.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	}

	{  // 1280 x 1024 60Hz (108 MHz)
		1280,1024,60,						// X/Y/Freq
		(1688-2) | (1280L << 16),		// HD Total + HD End
		(1066-1) | ((1024L-1) << 16), // VD Total + VD End
		1328 | (1440L << 16),			// HS Start + HS End
		1025 | (1028L << 16),			// VS Start + VS End
		//0x00b40b10,					// PLLx multiplier and control
		108.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	}

	{  // 1280 x 1024 75Hz (135 MHz)
		1280,1024,75,						// X/Y/Freq
		(1688-2) | (1280L << 16),		// HD Total + HD End
		(1066-1) | ((1024L-1) << 16),	// VD Total + VD End
		1296 | (1440L << 16),			// HS Start + HS End
		1025 | (1028L << 16),			// VS Start + VS End
		//0x00830610,					// PLLx multiplier and control
		135.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	}

	{  // 1280 x 1024 85Hz (157.5 MHz)
		1280,1024,85,						// X/Y/Freq
		(1728-2) | (1280L << 16),		// HD Total + HD End
		(1072-1) | ((1024L-1) << 16),	// VD Total + VD End
		1344 | (1504L << 16),			// HS Start + HS End
		1025 | (1028L << 16),			// VS Start + VS End
		//0x00f10a10,					// PLLx multiplier and control
		157.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	}
 #endif // No support for 95MHz or more
#else // Reference clock = 12.288 MHz
	{  // 640 x 480 60Hz (25.175 MHz)
		640,480,60,							// X/Y/Freq
		(800-2) | (640L << 16),      	// HD Total + HD End
		(525-1) | ((480L-1) << 16),	// VD Total + VD End
		656 | (752L << 16),				// HS Start + HS End
		490 | (492L << 16),				// VS Start + VS End
		//0x00a30930,					// PLLx multiplier and control
		25.175F,						// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 640 x 480 72Hz (31.5 MHz)
		640,480,72,							// X/Y/Freq
		(832-2) | (640L << 16),      	// HD Total + HD End
		(520-1) | ((480L-1) << 16),	// VD Total + VD End
		//664 | (704L << 16),				// HS Start + HS End
		688 | (728L << 16),				// HS Start + HS End
		489 | (492L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 640 x 480 75Hz (31.5 MHz)
		640,480,75,							// X/Y/Freq
		(840-2) | (640L << 16),      	// HD Total + HD End
		(500-1) | ((480L-1) << 16),	// VD Total + VD End
		//656 | (720L << 16),				// HS Start + HS End
		680 | (744L << 16),				// HS Start + HS End
		481 | (484L << 16),				// VS Start + VS End
		//0x00f50b30,					// PLLx multiplier and control
		31.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 640 x 480 85Hz (36 MHz)
		640,480,85,							// X/Y/Freq
		(832-2) | (640L << 16),      	// HD Total + HD End
		(509-1) | ((480L-1) << 16),	// VD Total + VD End
		696 | (752L << 16),				// HS Start + HS End
		481 | (484L << 16),				// VS Start + VS End
		//0x00d20830,					// PLLx multiplier and control
		36.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 800 x 600 60Hz (40 MHz)
		800,600,60,							// X/Y/Freq
		(1054-2) | (800L << 16),		// HD Total + HD End
		(628-1) | ((600L-1) << 16),	// VD Total + VD End
		839 | (967L << 16),				// HS Start + HS End
		601 | (605L << 16),				// VS Start + VS End
		//0x00e90830,					// PLLx multiplier and control
		40.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 800 x 600 72Hz 50 MHz)
		800,600,72,							// X/Y/Freq
		(1040-2) | (800L << 16),		// HD Total + HD End
		(666-1) | ((600L-1) << 16),	// VD Total + VD End
		856 | (976L << 16),				// HS Start + HS End
		637 | (643L << 16),				// VS Start + VS End
		//0x00b20a20,					// PLLx multiplier and control
		50.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 800 x 600 75Hz (49.5 MHz)
		800,600,75,							// X/Y/Freq
		(1056-2) | (800L << 16),		// HD Total + HD End
		(625-1) | ((600L-1) << 16),	// VD Total + VD End
		816 | (896L << 16),				// HS Start + HS End
		601 | (604L << 16),				// VS Start + VS End
		//0x00900820,					// PLLx multiplier and control
		49.5F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 800 x 600 85Hz (56.25 MHz)
		800,600,85,							// X/Y/Freq
		(1047-2) | (800L << 16),		// HD Total + HD End
		(631-1) | ((600L-1) << 16),	// VD Total + VD End
		832 | (896L << 16),				// HS Start + HS End
		601 | (604L << 16),				// VS Start + VS End
		//0x00b60920,					// PLLx multiplier and control
		56.25F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},
   
	{  // 1024 x 768 60Hz (65 MHz)
		1024,768,60,						// X/Y/Freq
		(1344-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1048 | (1184L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00fd0b20,					// PLLx multiplier and control
		65.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},			

	{  // 1024 x 768 70Hz (75 MHz)
		1024,768,70,						// X/Y/Freq
		(1327-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1047 | (1183L << 16),			// HS Start + HS End
		771 | (777L << 16),				// VS Start + VS End
		//0x00f30920,					// PLLx multiplier and control
		75.0F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD
	},

	{  // 1024 x 768 75Hz (78.750 MHz)
		1024,768,75,						// X/Y/Freq
		(1312-2) | (1024L << 16),		// HD Total + HD End
		(806-1) | ((768L-1) << 16),	// VD Total + VD End
		1040 | (1136L << 16),			// HS Start + HS End
		769 | (772L << 16),				// VS Start + VS End
		//0x00cc0720,					// PLLx multiplier and control
		78.75F,							// PLLx frequency
		//FDx_1 | (1 << 24),			// FDx and SD