gfx_regs.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#define DC_TCFG_FVSP        0x00000800      /* panel vert sync polarity */
#define DC_TCFG_FCEN        0x00001000      /* flat-panel centering     */
#define DC_TCFG_CDCE        0x00002000      /* HACK - 1.3 definition    */
#define DC_TCFG_PLNR        0x00002000      /* planar mode enable       */
#define DC_TCFG_INTL        0x00004000      /* interlace scan           */
#define DC_TCFG_PXDB        0x00008000      /* pixel double             */
#define DC_TCFG_BKRT        0x00010000      /* blink rate               */
#define DC_TCFG_PSD_MASK    0x000E0000      /* power sequence delay     */
#define DC_TCFG_PSD_POS     17              /* power sequence delay     */
#define DC_TCFG_DDCI        0x08000000      /* DDC input (RO)           */
#define DC_TCFG_SENS        0x10000000      /* monitor sense (RO)       */
#define DC_TCFG_DNA         0x20000000      /* display not active (RO)  */
#define DC_TCFG_VNA         0x40000000      /* vertical not active (RO) */
#define DC_TCFG_VINT        0x80000000      /* vertical interrupt (RO)  */

/* "DC_OUTPUT_CFG" BIT DEFINITIONS */

#define DC_OCFG_8BPP        0x00000001      /* 8/16 bpp select          */
#define DC_OCFG_555         0x00000002      /* 16 bpp format            */
#define DC_OCFG_PCKE        0x00000004      /* PCLK enable              */
#define DC_OCFG_FRME        0x00000008      /* frame rate mod enable    */
#define DC_OCFG_DITE        0x00000010      /* dither enable            */
#define DC_OCFG_2PXE        0x00000020      /* 2 pixel enable           */
#define DC_OCFG_2XCK        0x00000040      /* 2 x pixel clock          */
#define DC_OCFG_2IND        0x00000080      /* 2 index enable           */
#define DC_OCFG_34ADD       0x00000100      /* 3- or 4-bit add          */
#define DC_OCFG_FRMS        0x00000200      /* frame rate mod select    */
#define DC_OCFG_CKSL        0x00000400      /* clock select             */
#define DC_OCFG_PRMP        0x00000800      /* palette re-map           */
#define DC_OCFG_PDEL        0x00001000      /* panel data enable low    */
#define DC_OCFG_PDEH        0x00002000      /* panel data enable high   */
#define DC_OCFG_CFRW        0x00004000      /* comp line buffer r/w sel */
#define DC_OCFG_DIAG        0x00008000      /* comp line buffer diag    */

#define MC_DR_ADD           0x00008418
#define MC_DR_ACC           0x0000841C

/*----------*/
/*  CS5530  */
/*----------*/

/* CS5530 REGISTER DEFINITIONS */

#define CS5530_VIDEO_CONFIG         0x0000
#define CS5530_DISPLAY_CONFIG       0x0004
#define CS5530_VIDEO_X_POS          0x0008
#define CS5530_VIDEO_Y_POS          0x000C
#define CS5530_VIDEO_SCALE          0x0010
#define CS5530_VIDEO_COLOR_KEY      0x0014
#define CS5530_VIDEO_COLOR_MASK     0x0018
#define CS5530_PALETTE_ADDRESS      0x001C
#define CS5530_PALETTE_DATA         0x0020
#define CS5530_DOT_CLK_CONFIG       0x0024
#define CS5530_CRCSIG_TFT_TV        0x0028

/* "CS5530_VIDEO_CONFIG" BIT DEFINITIONS */

#define CS5530_VCFG_VID_EN                  0x00000001  
#define CS5530_VCFG_VID_REG_UPDATE          0x00000002  
#define CS5530_VCFG_VID_INP_FORMAT          0x0000000C  
#define CS5530_VCFG_8_BIT_4_2_0             0x00000004
#define CS5530_VCFG_16_BIT_4_2_0            0x00000008
#define CS5530_VCFG_GV_SEL                  0x00000010  
#define CS5530_VCFG_CSC_BYPASS              0x00000020  
#define CS5530_VCFG_X_FILTER_EN             0x00000040  
#define CS5530_VCFG_Y_FILTER_EN             0x00000080  
#define CS5530_VCFG_LINE_SIZE_LOWER_MASK    0x0000FF00  
#define CS5530_VCFG_INIT_READ_MASK          0x01FF0000  
#define CS5530_VCFG_EARLY_VID_RDY           0x02000000  
#define CS5530_VCFG_LINE_SIZE_UPPER         0x08000000  
#define CS5530_VCFG_4_2_0_MODE              0x10000000  
#define CS5530_VCFG_16_BIT_EN               0x20000000
#define CS5530_VCFG_HIGH_SPD_INT            0x40000000

/* "CS5530_DISPLAY_CONFIG" BIT DEFINITIONS */

#define CS5530_DCFG_DIS_EN                  0x00000001  
#define CS5530_DCFG_HSYNC_EN                0x00000002  
#define CS5530_DCFG_VSYNC_EN                0x00000004  
#define CS5530_DCFG_DAC_BL_EN               0x00000008  
#define CS5530_DCFG_DAC_PWDNX               0x00000020  
#define CS5530_DCFG_FP_PWR_EN               0x00000040  
#define CS5530_DCFG_FP_DATA_EN              0x00000080  
#define CS5530_DCFG_CRT_HSYNC_POL           0x00000100  
#define CS5530_DCFG_CRT_VSYNC_POL           0x00000200  
#define CS5530_DCFG_FP_HSYNC_POL            0x00000400  
#define CS5530_DCFG_FP_VSYNC_POL            0x00000800  
#define CS5530_DCFG_XGA_FP                  0x00001000  
#define CS5530_DCFG_FP_DITH_EN              0x00002000  
#define CS5530_DCFG_CRT_SYNC_SKW_MASK       0x0001C000
#define CS5530_DCFG_CRT_SYNC_SKW_INIT       0x00010000
#define CS5530_DCFG_PWR_SEQ_DLY_MASK        0x000E0000
#define CS5530_DCFG_PWR_SEQ_DLY_INIT        0x00080000
#define CS5530_DCFG_VG_CK                   0x00100000
#define CS5530_DCFG_GV_PAL_BYP              0x00200000
#define CS5530_DCFG_DDC_SCL                 0x00400000
#define CS5530_DCFG_DDC_SDA                 0x00800000
#define CS5530_DCFG_DDC_OE                  0x01000000
#define CS5530_DCFG_16_BIT_EN               0x02000000

/*----------*/
/*  SC1400  */
/*----------*/

/* SC1400 VIDEO REGISTER DEFINITIONS */

#define SC1400_VIDEO_CONFIG                 0x000
#define SC1400_DISPLAY_CONFIG               0x004
#define SC1400_VIDEO_X_POS                  0x008
#define SC1400_VIDEO_Y_POS                  0x00C
#define SC1400_VIDEO_SCALE                  0x010
#define SC1400_VIDEO_COLOR_KEY              0x014
#define SC1400_VIDEO_COLOR_MASK             0x018
#define SC1400_PALETTE_ADDRESS              0x01C
#define SC1400_PALETTE_DATA                 0x020
#define SC1400_VID_MISC                     0x028
#define SC1400_VID_CLOCK_SELECT             0x02C
#define SC1400_VID_CRC                      0x044
#define SC1400_TVOUT_HORZ_TIM               0x800
#define SC1400_TVOUT_HORZ_SYNC              0x804
#define SC1400_TVOUT_VERT_SYNC              0x808
#define SC1400_TVOUT_LINE_END               0x80C
#define SC1400_TVOUT_VERT_DOWNSCALE         0x810
#define SC1400_TVOUT_HORZ_SCALING           0x814
#define SC1400_TVOUT_EMMA_BYPASS            0x81C
#define SC1400_TVENC_TIM_CTRL_1             0xC00
#define SC1400_TVENC_TIM_CTRL_2             0xC04
#define SC1400_TVENC_TIM_CTRL_3             0xC08
#define SC1400_TVENC_SUB_FREQ               0xC0C
#define SC1400_TVENC_DISP_POS               0xC10
#define SC1400_TVENC_DISP_SIZE              0xC14
#define SC1400_TVENC_CC_DATA                0xC18
#define SC1400_TVENC_EDS_DATA               0xC1C
#define SC1400_TVENC_CGMS_DATA              0xC20
#define SC1400_TVENC_WSS_DATA               0xC24
#define SC1400_TVENC_CC_CONTROL             0xC28
#define SC1400_TVENC_DAC_CONTROL            0xC2C

/* "SC1400_VIDEO_CONFIG" BIT DEFINITIONS */

#define SC1400_VCFG_VID_EN                  0x00000001  
#define SC1400_VCFG_VID_REG_UPDATE          0x00000002  
#define SC1400_VCFG_VID_INP_FORMAT          0x0000000C  
#define SC1400_VCFG_8_BIT_4_2_0             0x00000004
#define SC1400_VCFG_16_BIT_4_2_0            0x00000008
#define SC1400_VCFG_GV_SEL                  0x00000010  
#define SC1400_VCFG_CSC_BYPASS              0x00000020  
#define SC1400_VCFG_X_FILTER_EN             0x00000040  
#define SC1400_VCFG_Y_FILTER_EN             0x00000080  
#define SC1400_VCFG_LINE_SIZE_LOWER_MASK    0x0000FF00  
#define SC1400_VCFG_INIT_READ_MASK          0x01FF0000  
#define SC1400_VCFG_EARLY_VID_RDY           0x02000000  
#define SC1400_VCFG_LINE_SIZE_UPPER         0x08000000  
#define SC1400_VCFG_4_2_0_MODE              0x10000000  
#define SC1400_VCFG_16_BIT_EN               0x20000000
#define SC1400_VCFG_HIGH_SPD_INT            0x40000000

/* "SC1400_DISPLAY_CONFIG" BIT DEFINITIONS */

#define SC1400_DCFG_DIS_EN                  0x00000001  
#define SC1400_DCFG_HSYNC_EN                0x00000002  
#define SC1400_DCFG_VSYNC_EN                0x00000004  
#define SC1400_DCFG_DAC_BL_EN               0x00000008  
#define SC1400_DCFG_DAC_PWDNX               0x00000020  
#define SC1400_DCFG_TVOUT_EN                0x000000C0  
#define SC1400_DCFG_CRT_HSYNC_POL           0x00000100  
#define SC1400_DCFG_CRT_VSYNC_POL           0x00000200  
#define SC1400_DCFG_FP_HSYNC_POL            0x00000400  
#define SC1400_DCFG_FP_VSYNC_POL            0x00000800  
#define SC1400_DCFG_XGA_FP                  0x00001000  
#define SC1400_DCFG_FP_DITH_EN              0x00002000  
#define SC1400_DCFG_CRT_SYNC_SKW_MASK       0x0001C000
#define SC1400_DCFG_CRT_SYNC_SKW_INIT       0x00010000
#define SC1400_DCFG_PWR_SEQ_DLY_MASK        0x000E0000
#define SC1400_DCFG_PWR_SEQ_DLY_INIT        0x00080000
#define SC1400_DCFG_VG_CK                   0x00100000
#define SC1400_DCFG_GV_PAL_BYP              0x00200000
#define SC1400_DCFG_DDC_SCL                 0x00400000
#define SC1400_DCFG_DDC_SDA                 0x00800000
#define SC1400_DCFG_DDC_OE                  0x01000000
#define SC1400_DCFG_16_BIT_EN               0x02000000

/* SC1400 VIP REGISTER DEFINITIONS */

#define SC1400_VIP_CONFIG                   0x00000000
#define SC1400_VIP_CONTROL                  0x00000004
#define SC1400_VIP_STATUS                   0x00000008
#define SC1400_VIP_CURRENT_LINE             0x00000010
#define SC1400_VIP_LINE_TARGET              0x00000014
#define SC1400_VIP_ODD_BASE                 0x00000020
#define SC1400_VIP_EVEN_BASE                0x00000024
#define SC1400_VIP_PITCH                    0x00000028
#define SC1400_VBI_ODD_BASE                 0x00000040
#define SC1400_VBI_EVEN_BASE                0x00000044
#define SC1400_VBI_PITCH                    0x00000048

/* "SC1400_VIP_CONTROL" BIT DEFINITIONS */

#define SC1400_VIP_DATA_CAPTURE_EN          0x00000100
#define SC1400_VIP_VBI_CAPTURE_EN           0x00000200

/* SC1400 CONFIGURATION BLOCK */

#define SC1400_CB_BASE_ADDR                 0x9000