cy_regs.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*
 * $Workfile: CY_REGS.H $
 * $Revision: 4 $
 * $Date: 4/07/00 8:48a $
 * $Modtime: 4/07/00 8:38a $
 * $Author: Sarma $
 *
 * Register addresses associated with the GXi, GXm, AND MXi.
 *
 * Copyright (c) 1998 National Semiconductor Corporation.
 * All Rights Reserved.
 *
 * This software is the confidential and proprietary information of National 
 * Semiconductor Corporation. ("Confidential Information").
 * You shall not disclose such Confidential Information and shall use it only
 * in accordance with the terms of the license agreement you entered into
 * with National Semiconductor Corporation.
 * This code is supplied as is.
 *
 */

/*
 *$Log: /CE/Platform/Nsc/Drivers/Video/gxvideo/base/CY_REGS.H $
 * 
 * 4     4/07/00 8:48a Sarma
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * 3     3/29/00 9:15a Sarma
 * Adding necessary include files depending upon the env variables set for
 * direct draw. Dhruva regs are now being used only for directdraw.
 * 
 * 2     11/12/98 3:14p Sarma
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
 *$History: CY_REGS.H $
 * 
 * *****************  Version 4  *****************
 * User: Sarma        Date: 4/07/00    Time: 8:48a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * *****************  Version 3  *****************
 * User: Sarma        Date: 3/29/00    Time: 9:15a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Adding necessary include files depending upon the env variables set for
 * direct draw. Dhruva regs are now being used only for directdraw.
 * 
 * *****************  Version 2  *****************
 * User: Sarma        Date: 11/12/98   Time: 3:14p
 * Updated in $/wince/v2.1/gxvideo
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
*/

#ifndef CY_REGS_H

#define CY_REGS_H

/**************************************************************************/
//VGA REGISTERS

#define MISCOUT_WR         0x3C2
#define MISCOUT_RD         0x3CC
#define ISR_0              0x3C2
#define ISR_1_M            0x3ba
#define ISR_1_C            0x3da
#define FEAT_CTRL_R        0x3CA
#define FEAT_CTRL_M_WR     0x3BA
#define FEAT_CTRL_C_WR     0x3DA
#define TS_INDEX           0x3C4
#define TS_DATA            0x3C5
#define CRTC_INDEX_C       0x3D4
#define CRTC_INDEX_M       0x3B4
#define CRTC_DATA_C        0x3d5
#define CRTC_DATA_M        0x3b5
#define GDC_INDEX          0x3CE
#define GDC_DATA           0x3cf
#define ATC_INDEX          0x3C0
#define ATC_DATA_READ      0x3C1
#define ATC_DATA_WRITE     0x3C0


/*
 * Internal TS register addresses
 */
#define   SEQ_RESET            0
#define   SEQ_CLOCK_MODE       1
#define   SEQ_MAP_MASK         2
#define   SEQ_CHAR_MAP_SEL     3
#define   SEQ_MEMORY_MODE      4

/*
 * Internal CRTC addresses
 */
#define   CRTC_HTOT                     0
#define   CRTC_HBLK_DISP                1
#define   CRTC_HBLK_START               2
#define   CRTC_HBLK_END                 3
#define   CRTC_HSYNC_START              4
#define   CRTC_HSYNC_END                5
#define   CRTC_VTOT                     6
#define   CRTC_OVERFLOW                 7
#define   CRTC_PRESET                   8
#define   CRTC_MAX_SCAN                 9
#define   CRTC_CUR_START                0xA
#define   CRTC_CUR_END                  0xB
#define   CRTC_START_HIGH               0xC
#define   CRTC_START_LOW                0xD
#define   CRTC_CUR_HIGH                 0xE
#define   CRTC_CUR_LOW                  0xF
#define   CRTC_VSYNC_START              0x10
#define   CRTC_VSYNC_END                0x11
#define   CRTC_VDISP_END                0x12
#define   CRTC_OFFSET                   0x13
#define   CRTC_UNDERLINE                0x14
#define   CRTC_VBLK_START               0x15
#define   CRTC_VBLK_END                 0x16
#define   CRTC_MODE                     0x17
#define   CRTC_LINE_COMP                0x18
#define   CRTC_CPU_DATA_LAT             0x22
#define   CRTC_ATTR_DATA_INDEX          0x24
#define   CRTC_ATTR_INDEX_ST            0x26

//Extended CRTC registers   (partial)
#define     CRTC_EXT_REG_LOCK          0x30
#define     CRTC_SOFT_VGA_REV          0x31
#define     CRTC_DISP_DATA_CH          0x32
#define     CRTC_DISP_STATUS           0x33
#define     CRTC_DDRAW_MEM_BASE        0x3C
#define     CRTC_DDRAW_MEM_SIZE        0x3D
#define     CRTC_GRAPH_MEM_SIZE        0x3E
#define     CRTC_MODE_SW               0x3F


/*
 * Internal GC addresses
 */
#define   GDC_SET_RESET         0
#define   GDC_ENABLE_SR         1
#define   GDC_CCOMPARE          2
#define   GDC_DROTATE           3
#define   GDC_READ_MAP          4
#define   GDC_GRAPHICS          5
#define   GDC_MISC              6
#define   GDC_CNO_CARE          7
#define   GDC_BIT_MASK          8

/*
 * Internal ATC addresses
 */
#define   ATC_MODE_CTRL         0x10
#define   ATC_OVERSCAN          0x11
#define   ATC_COLOR_PLANE       0x12
#define   ATC_HPAN              0x13
#define   ATC_COLOR_SELECT      0x14

/*
 * External Pal address
 */
#define   RD_DAC                0x3C7
#define   WR_DAC                0x3C8
#define   DAC_DATA              0x3C9
#define   PEL_RD                0x3C6
#define   PEL_WR                0x3C6

/**************************************************************************/
// GXx CONFIGURATION REGISTERS

#define CONFIG_PCR              0x20
#define CONFIG_CCR1             0xC1
#define CONFIG_CCR2             0xC2
#define CONFIG_CCR3             0xC3
#define CONFIG_CCR4             0xE8
#define CONFIG_DIR0             0xFE
#define CONFIG_DIR1             0xFF
#define CONFIG_SMAR0            0xCD
#define CONFIG_SMAR1            0xCE
#define CONFIG_SMAR2            0xCF
#define CONFIG_SMHR0            0xB0
#define CONFIG_SMHR1            0xB1
#define CONFIG_SMHR2            0xB2
#define CONFIG_SMHR3            0xB3
#define CONFIG_GCR              0xB8
#define CONFIG_VGACTL           0xB9
#define CONFIG_VGAM0            0xBA
#define CONFIG_VGAM1            0xBB
#define CONFIG_VGAM2            0xBC
#define CONFIG_VGAM3            0xBD


/**************************************************************************/
// GXx DISPLAY CONTROLLER REGISTERS

#define DC_UNLOCK               0x8300  
#define DC_GENERAL_CFG          0x8304
#define DC_TIMING_CFG           0x8308
#define DC_OUTPUT_CFG           0x830C
#define DC_FB_ST_OFFSET         0x8310
#define DC_CB_ST_OFFSET         0x8314
#define DC_CURS_ST_OFFSET       0x8318
#define DC_VID_ST_OFFSET        0x8320
#define DC_LINE_DELTA           0x8324
#define DC_BUF_SIZE             0x8328
#define DC_H_TIMING_1           0x8330
#define DC_H_TIMING_2           0x8334
#define DC_H_TIMING_3           0x8338
#define DC_FP_H_TIMING          0x833C
#define DC_V_TIMING_1           0x8340
#define DC_V_TIMING_2           0x8344
#define DC_V_TIMING_3           0x8348
#define DC_FP_V_TIMING          0x834C
#define DC_CURSOR_X             0x8350
#define DC_V_LINE_CNT           0x8354
#define DC_CURSOR_Y             0x8358
#define DC_SS_LINE_CMP          0x835C
#define DC_CURSOR_COLOR         0x8360
#define DC_BORDER_COLOR         0x8368
#define DC_PAL_ADDRESS          0x8370
#define DC_PAL_DATA             0x8374
#define DC_DFIFO_DIAG           0x8378
#define DC_CFIFO_DIAG           0x837C

/**************************************************************************/
// 55xx VIDEO CONTROLLER REGISTERS

#define CX55xx_VIDEO_CONFIG         0x00
#define CX55xx_DISPLAY_CONFIG       0x04
#define CX55xx_VIDEO_X_POS          0x08
#define CX55xx_VIDEO_Y_POS          0x0C
#define CX55xx_VIDEO_SCALE          0x10
#define CX55xx_VIDEO_COLOR_KEY      0x14
#define CX55xx_VIDEO_COLOR_MASK     0x18
#define CX55xx_PALETTE_ADDRESS      0x1C
#define CX55xx_PALETTE_DATA         0x20
#define CX55xx_DOT_CLK_CONFIG       0x24

#ifdef DD_SUPPORT
#include <dhruva_regs.h>
#endif

#endif //CY_REGS_H