📄 gxdefs.h
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#define DC_PAL_ADDRESS 0x8370 /* palette address */
#define DC_PAL_DATA 0x8374 /* palette data */
/*-------------------------------*/
/* PALETTE ADDRESS DEFINITIONS */
/*-------------------------------*/
#define PAL_CURSOR_COLOR_0 0x100
#define PAL_CURSOR_COLOR_1 0x101
#define PAL_ICON_COLOR_0 0x102
#define PAL_ICON_COLOR_1 0x103
#define PAL_OVERSCAN_COLOR 0x104
/*----------------------*/
/* DC BIT DEFINITIONS */
/*----------------------*/
#define DC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */
#define DC_GCFG_DFLE 0x00000001 /* display FIFO load enable */
#define DC_GCFG_CURE 0x00000002 /* cursor enable */
#define DC_GCFG_PLNO 0x00000004 /* planar offset LSB */
#define DC_GCFG_PPC 0x00000008 /* pixel pan compatibility */
#define DC_GCFG_CMPE 0x00000010 /* compression enable */
#define DC_GCFG_DECE 0x00000020 /* decompression enable */
#define DC_GCFG_DCLK_MASK 0x000000C0 /* dotclock multiplier */
#define DC_GCFG_DCLK_POS 6 /* dotclock multiplier */
#define DC_GCFG_DFHPSL_MASK 0x00000F00 /* FIFO high-priority start */
#define DC_GCFG_DFHPSL_POS 8 /* FIFO high-priority start */
#define DC_GCFG_DFHPEL_MASK 0x0000F000 /* FIFO high-priority end */
#define DC_GCFG_DFHPEL_POS 12 /* FIFO high-priority end */
#define DC_GCFG_CIM_MASK 0x00030000 /* compressor insert mode */
#define DC_GCFG_CIM_POS 16 /* compressor insert mode */
#define DC_GCFG_FDTY 0x00040000 /* frame dirty mode */
#define DC_GCFG_RTPM 0x00080000 /* real-time perf. monitor */
#define DC_GCFG_DAC_RS_MASK 0x00700000 /* DAC register selects */
#define DC_GCFG_DAC_RS_POS 20 /* DAC register selects */
#define DC_GCFG_CKWR 0x00800000 /* clock write */
#define DC_GCFG_LDBL 0x01000000 /* line double */
#define DC_GCFG_DIAG 0x02000000 /* FIFO diagnostic mode */
#define DC_GCFG_CH4S 0x04000000 /* sparse refresh mode */
#define DC_GCFG_SSLC 0x08000000 /* enable line compare */
#define DC_GCFG_VIDE 0x10000008 /* video enable */
#define DC_GCFG_DFCK 0x20000000 /* divide flat-panel clock - rev 2.3 down */
#define DC_GCFG_VRDY 0x20000000 /* video port speed - rev 2.4 up */
#define DC_GCFG_DPCK 0x40000000 /* divide pixel clock */
#define DC_GCFG_DDCK 0x80000000 /* divide dot clock */
#define DC_TCFG_FPPE 0x00000001 /* flat-panel power enable */
#define DC_TCFG_HSYE 0x00000002 /* horizontal sync enable */
#define DC_TCFG_VSYE 0x00000004 /* vertical sync enable */
#define DC_TCFG_BLKE 0x00000008 /* blank enable */
#define DC_TCFG_DDCK 0x00000010 /* DDC clock */
#define DC_TCFG_TGEN 0x00000020 /* timing generator enable */
#define DC_TCFG_VIEN 0x00000040 /* vertical interrupt enable*/
#define DC_TCFG_BLNK 0x00000080 /* blink enable */
#define DC_TCFG_CHSP 0x00000100 /* horizontal sync polarity */
#define DC_TCFG_CVSP 0x00000200 /* vertical sync polarity */
#define DC_TCFG_FHSP 0x00000400 /* panel horz sync polarity */
#define DC_TCFG_FVSP 0x00000800 /* panel vert sync polarity */
#define DC_TCFG_FCEN 0x00001000 /* flat-panel centering */
#define DC_TCFG_CDCE 0x00002000 /* HACK - 1.3 definition */
#define DC_TCFG_PLNR 0x00002000 /* planar mode enable */
#define DC_TCFG_INTL 0x00004000 /* interlace scan */
#define DC_TCFG_PXDB 0x00008000 /* pixel double */
#define DC_TCFG_BKRT 0x00010000 /* blink rate */
#define DC_TCFG_PSD_MASK 0x000E0000 /* power sequence delay */
#define DC_TCFG_PSD_POS 17 /* power sequence delay */
#define DC_TCFG_DDCI 0x08000000 /* DDC input (RO) */
#define DC_TCFG_SENS 0x10000000 /* monitor sense (RO) */
#define DC_TCFG_DNA 0x20000000 /* display not active (RO) */
#define DC_TCFG_VNA 0x40000000 /* vertical not active (RO) */
#define DC_TCFG_VINT 0x80000000 /* vertical interrupt (RO) */
#define DC_OCFG_8BPP 0x00000001 /* 8/16 bpp select */
#define DC_OCFG_555 0x00000002 /* 16 bpp format */
#define DC_OCFG_PCKE 0x00000004 /* PCLK enable */
#define DC_OCFG_FRME 0x00000008 /* frame rate mod enable */
#define DC_OCFG_DITE 0x00000010 /* dither enable */
#define DC_OCFG_2PXE 0x00000020 /* 2 pixel enable */
#define DC_OCFG_2XCK 0x00000040 /* 2 x pixel clock */
#define DC_OCFG_2IND 0x00000080 /* 2 index enable */
#define DC_OCFG_34ADD 0x00000100 /* 3- or 4-bit add */
#define DC_OCFG_FRMS 0x00000200 /* frame rate mod select */
#define DC_OCFG_CKSL 0x00000400 /* clock select */
#define DC_OCFG_PRMP 0x00000800 /* palette re-map */
#define DC_OCFG_PDEL 0x00001000 /* panel data enable low */
#define DC_OCFG_PDEH 0x00002000 /* panel data enable high */
#define DC_OCFG_CFRW 0x00004000 /* comp line buffer r/w sel */
#define DC_OCFG_DIAG 0x00008000 /* comp line buffer diag */
#define DC_VID_BUF_SZ_MASK 0x3FFF0000 /* video buffer size in 64KB segments */
#define DC_VID_BUF_SZ_POS 16 /* max. of 1MB */
/*---------------------------*/
/* BC REGISTER DEFINITIONS */
/*---------------------------*/
#define BC_XMAP_1 0x8004
#define BC_XMAP_2 0x8008
#define BC_XMAP_3 0x800c
/*----------------------*/
/* BC BIT DEFINITIONS */
/*----------------------*/
#define BC_X1_A_MASK 0x0000000F /* Region A control field */
#define BC_X1_A_POS 0 /* Region A control field */
#define BC_X1_GEA 0x00000010 /* Region A graphics enable */
#define BC_X1_XNWS 0x00000020 /* X-bus no wait state */
#define BC_X1_GNWS 0x00000040 /* X-bus graphics no wait state */
#define BC_X1_XPD 0x00000080 /* X-bus pipeline disable */
#define BC_X1_SMIB 0x00002000 /* SMI enable I/O ports 3Bx */
#define BC_X1_SMIC 0x00004000 /* SMI enable I/O ports 3Cx */
#define BC_X1_SMID 0x00008000 /* SMI enable I/O ports 3Dx */
#define BC_X1_B0_MASK 0x000F0000 /* Region B0 control field */
#define BC_X1_B0_POS 16 /* Region B0 control field */
#define BC_X1_GEB0 0x00100000 /* Region B0 graphics enable */
#define BC_X1_A20M 0x00200000 /* A20 mask */
#define BC_X1_PRAE 0x00400000 /* PCI register access enable */
#define BC_X1_8M 0x00800000 /* Enable PCI 8M hole */
#define BC_X1_B8_MASK 0x0F000000 /* Region B8 control field */
#define BC_X1_B8_POS 24 /* Region B8 control field */
#define BC_X1_GEB8 0x10000000 /* Region B8 graphics enable */
/*---------------------------*/
/* MC REGISTER DEFINITIONS */
/*---------------------------*/
#define MC_MEM_CNTRL1 0x8400 /* Memory control register */
#define MC_MEM_CNTRL2 0x8404 /* Memory/L2 cache control */
#define MC_BANK_ADD 0x8408 /* Memory bank address */
#define MC_ASYNC_TIM1 0x840C /* Memory timing register 1 */
#define MC_ASYNC_TIM2 0x8410 /* Memory timing register 2 */
#define MC_GBASE_ADD 0x8414 /* Graphics memory base address */
#define MC_DR_ADD 0x8418 /* Dirty RAM address index */
#define MC_DR_ACC 0x841C /* Dirty RAM memory access */
#define MC_RAMDAC_ACC 0x8420 /* RAMDAC register access */
#define MC_STRAP 0x8424 /* Reset strap values */
/*---------------------------*/
/* PM REGISTER DEFINITIONS */
/*---------------------------*/
#define PM_CNTRL_SMI 0x8500 /* SMI status */
#define PM_CNTRL_TEN 0x8504 /* Transmission enable control */
#define PM_CNTRL_CSTP 0x8508 /* Clock stop */
#define PM_SER_PACK 0x850C /* Serial packet data */
/*-------------------------------------*/
/* CPU REGISTER REGISTER DEFINITIONS */
/*-------------------------------------*/
#define GX_BB0_BASE 0xFFFFFF0C /* Blit buffer 0 base */
#define GX_BB1_BASE 0xFFFFFF1C /* Blit buffer 1 base */
#define BB0_POINTER 0xFFFFFF2C /* Index into blit buffer 0 */
#define BB1_POINTER 0xFFFFFF3C /* Index into blit buffer 1 */
#define PM_BASE 0xFFFFFF6C /* Power management base */
#define PM_MASK 0xFFFFFF7C /* Power management address mask */
/*---------------------*/
/* RASTER OPERATIONS */
/*---------------------*/
#define GX_BLACKNESS 0x00000 /* Set destination to black */
#define GX_DSTINVERT 0x00055 /* Reverse bits in destination */
#define GX_SRCCOPY 0x000CC /* Copy source to destination */
#define GX_PATCOPY 0x000F0 /* Copy pattern to destination */
#define GX_WHITENESS 0x000FF /* Set destination to white */
/**************************************************************************/
// GXx CONFIGURATION REGISTERS
#define CONFIG_PCR 0x20
#define CONFIG_CCR1 0xC1
#define CONFIG_CCR2 0xC2
#define CONFIG_CCR3 0xC3
#define CONFIG_CCR4 0xE8
#define CONFIG_DIR0 0xFE
#define CONFIG_DIR1 0xFF
#define CONFIG_SMAR0 0xCD
#define CONFIG_SMAR1 0xCE
#define CONFIG_SMAR2 0xCF
#define CONFIG_SMHR0 0xB0
#define CONFIG_SMHR1 0xB1
#define CONFIG_SMHR2 0xB2
#define CONFIG_SMHR3 0xB3
#define CONFIG_GCR 0xB8
#define CONFIG_VGACTL 0xB9
#define CONFIG_VGAM0 0xBA
#define CONFIG_VGAM1 0xBB
#define CONFIG_VGAM2 0xBC
#define CONFIG_VGAM3 0xBD
/* END OF FILE */
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