gxdefs.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*
 * $Workfile: GXDEFS.H $
 * $Revision: 4 $
 * $Date: 4/07/00 8:50a $
 * $Modtime: 4/07/00 8:39a $
 * $Author: Sarma $
 *
 * This module performs miscellaneous support functions.
 *
 * Copyright (c) 1998 National Semiconductor Corporation.
 * All Rights Reserved.
 *
 * This software is the confidential and proprietary information of National 
 * Semiconductor Corporation. ("Confidential Information").
 * You shall not disclose such Confidential Information and shall use it only
 * in accordance with the terms of the license agreement you entered into
 * with National Semiconductor Corporation.
 * This code is supplied as is.
 *
 */

/*
 *$Log: /CE/Platform/Nsc/Drivers/Video/gxvideo/base/GXDEFS.H $
 * 
 * 4     4/07/00 8:50a Sarma
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * 3     3/29/00 9:30a Sarma
 * Using the latest file got from longmont.
 * 
 * 2     11/12/98 3:19p Sarma
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
 *$History: GXDEFS.H $
 * 
 * *****************  Version 4  *****************
 * User: Sarma        Date: 4/07/00    Time: 8:50a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * *****************  Version 3  *****************
 * User: Sarma        Date: 3/29/00    Time: 9:30a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Using the latest file got from longmont.
 * 
 * *****************  Version 2  *****************
 * User: Sarma        Date: 11/12/98   Time: 3:19p
 * Updated in $/wince/v2.1/gxvideo
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
*/

#define GX_CX55xx_OFFSET        0x10000     /* CX55xx offset for a GX */


/*---------------------------*/
/*  GP REGISTER DEFINITIONS  */
/*---------------------------*/

#define GP_DST_XCOOR            0x8100      /* x destination origin     */
#define GP_DST_YCOOR            0x8102      /* y destination origin     */
#define GP_WIDTH                0x8104      /* pixel width              */
#define GP_HEIGHT               0x8106      /* pixel height             */
#define GP_SRC_XCOOR            0x8108      /* x source origin          */
#define GP_SRC_YCOOR            0x810A      /* y source origin          */

#define GP_VECTOR_LENGTH        0x8104      /* vector length            */
#define GP_INIT_ERROR           0x8106      /* vector initial error     */
#define GP_AXIAL_ERROR          0x8108      /* axial error increment    */
#define GP_DIAG_ERROR           0x810A      /* diagonal error increment */

#define GP_SRC_COLOR_0          0x810C      /* source color 0           */
#define GP_SRC_COLOR_1          0x810E      /* source color 1           */
#define GP_PAT_COLOR_0          0x8110      /* pattern color 0          */
#define GP_PAT_COLOR_1          0x8112      /* pattern color 1          */
#define GP_PAT_COLOR_2          0x8114      /* pattern color 2          */
#define GP_PAT_COLOR_3          0x8116      /* pattern color 3          */
#define GP_PAT_DATA_0           0x8120      /* bits 31:0 of pattern     */
#define GP_PAT_DATA_1           0x8124      /* bits 63:32 of pattern    */
#define GP_PAT_DATA_2           0x8128      /* bits 95:64 of pattern    */
#define GP_PAT_DATA_3           0x812C      /* bits 127:96 of pattern   */

#define GP_VGA_WRITE            0x8140      /* VGA write path control   */
#define GP_VGA_READ             0x8144      /* VGA read path control    */

#define GP_RASTER_MODE          0x8200      /* raster operation         */
#define GP_VECTOR_MODE          0x8204      /* vector mode register     */
#define GP_BLIT_MODE            0x8208      /* blit mode register       */
#define GP_BLIT_STATUS          0x820C      /* blit status register     */

#define GP_VGA_BASE             0x8210      /* VGA memory offset (x64K) */
#define GP_VGA_LATCH            0x8214      /* VGA display latch        */

/*---------------------------------------------*/
/*  REGISTER BIT DEFINITIONS:  GX_VECTOR_MODE  */
/*---------------------------------------------*/

#define VM_X_MAJOR              0x0000      /* X major vector           */
#define VM_Y_MAJOR              0x0001      /* Y major vector           */
#define VM_MAJOR_INC            0x0002      /* positive major axis step */
#define VM_MINOR_INC            0x0004      /* positive minor axis step */
#define VM_READ_DST_FB          0x0008      /* read destination data    */

/*---------------------------------------------*/
/*  REGISTER BIT DEFINITIONS:  GX_RASTER_MODE  */
/*---------------------------------------------*/

#define RM_PAT_DISABLE          0x0000      /* pattern is disabled      */
#define RM_PAT_MONO             0x0100      /* 1BPP pattern expansion   */
#define RM_PAT_DITHER           0x0200      /* 2BPP pattern expansion   */
#define RM_PAT_COLOR            0x0300      /* 8BPP or 16BPP pattern    */
#define RM_PAT_MASK             0x0300      /* mask for pattern mode    */
#define RM_PAT_TRANSPARENT      0x0400      /* transparent 1BPP pattern */
#define RM_SRC_TRANSPARENT      0x0800      /* transparent 1BPP source  */
#define RM_CLIP_ENABLE          0x1000      /* enables clipping     */

#define RM_SRC_COPY             0xCC        /* source copy      */
#define RM_PAT_COPY             0xF0        /* source copy      */

/*---------------------------------------------*/
/*  REGISTER BIT DEFINITIONS:  GX_BLIT_STATUS  */
/*---------------------------------------------*/

#define BS_BLIT_BUSY            0x0001      /* blit engine is busy      */
#define BS_PIPELINE_BUSY        0x0002      /* graphics pipeline is busy*/
#define BS_BLIT_PENDING         0x0004      /* blit pending             */
#define BC_FLUSH                0x0080      /* flush pipeline requests  */
#define BC_8BPP                 0x0000      /* 8BPP mode                */
#define BC_16BPP                0x0100      /* 16BPP mode               */
#define BC_FB_WIDTH_1024        0x0000      /* framebuffer width = 1024 */
#define BC_FB_WIDTH_2048        0x0200      /* framebuffer width = 2048 */

/*-------------------------------------------*/
/*  REGISTER BIT DEFINITIONS:  GX_BLIT_MODE  */
/*-------------------------------------------*/

#define BM_READ_SRC_NONE        0x0000      /* source foreground color  */
#define BM_READ_SRC_FB          0x0001      /* read source from FB      */
#define BM_READ_SRC_BB0         0x0002      /* read source from BB0     */
#define BM_READ_SRC_BB1         0x0003      /* read source from BB1     */
#define BM_READ_SRC_MASK        0x0003      /* read source mask         */

#define BM_READ_DST_NONE        0x0000      /* no destination data      */
#define BM_READ_DST_BB0         0x0008      /* destination from BB0     */
#define BM_READ_DST_BB1         0x000C      /* destination from BB1     */
#define BM_READ_DST_FB0         0x0010      /* dest from FB (store BB0) */
#define BM_READ_DST_FB1         0x0014      /* dest from FB (store BB1) */
#define BM_READ_DST_MASK        0x001C      /* read destination mask    */

#define BM_WRITE_FB             0x0000      /* write to framebuffer     */
#define BM_WRITE_MEM            0x0020      /* write to memory          */
#define BM_WRITE_MASK           0x0020      /* write mask               */

#define BM_SOURCE_COLOR         0x0000      /* source is 8BPP or 16BPP  */
#define BM_SOURCE_EXPAND        0x0040      /* source is 1BPP           */
#define BM_SOURCE_TEXT          0x00C0      /* source is 1BPP text      */
#define BM_SOURCE_MASK          0x00C0      /* source mask              */

#define BM_REVERSE_Y            0x0100      /* reverse Y direction      */

/*---------------------------*/
/*  DC REGISTER DEFINITIONS  */
/*---------------------------*/

#define DC_UNLOCK               0x8300      /* lock register            */
#define DC_GENERAL_CFG          0x8304      /* config registers...      */
#define DC_TIMING_CFG           0x8308
#define DC_OUTPUT_CFG           0x830C

#define DC_FB_ST_OFFSET         0x8310      /* framebuffer start offset */
#define DC_CB_ST_OFFSET         0x8314      /* compression start offset */
#define DC_CURS_ST_OFFSET       0x8318      /* cursor start offset      */
#define DC_ICON_ST_OFFSET       0x831C      /* icon start offset        */
#define DC_VID_ST_OFFSET        0x8320      /* video start offset       */
#define DC_LINE_DELTA           0x8324      /* fb and cb skip counts    */
#define DC_BUF_SIZE             0x8328      /* fb and cb line size      */

#define DC_H_TIMING_1           0x8330      /* horizontal timing...     */
#define DC_H_TIMING_2           0x8334
#define DC_H_TIMING_3           0x8338
#define DC_FP_H_TIMING          0x833C

#define DC_V_TIMING_1           0x8340      /* vertical timing...       */
#define DC_V_TIMING_2           0x8344
#define DC_V_TIMING_3           0x8348
#define DC_FP_V_TIMING          0x834C

#define DC_CURSOR_X             0x8350      /* cursor x position        */
#define DC_ICON_X               0x8354      /* HACK - 1.3 definition    */
#define DC_V_LINE_CNT           0x8354      /* vertical line counter    */
#define DC_CURSOR_Y             0x8358      /* cursor y position        */
#define DC_ICON_Y               0x835C      /* HACK - 1.3 definition    */
#define DC_SS_LINE_COMPARE      0x835C      /* line compare value       */

#define DC_CURSOR_COLOR         0x8360      /* cursor colors            */
#define DC_ICON_COLOR           0x8364      /* icon colors              */
#define DC_BORDER_COLOR         0x8368      /* border color             */