cognac.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*
 * $Workfile: cognac.h $
 * $Revision: 2 $
 * $Date: 4/07/00 9:10a $
 * $Modtime: 4/07/00 9:01a $
 * $Author: Sarma $
 *
 *  DESCRIPTION: Cognac hardware registers and bit definitions for
 *               the National display driver.
 *
 * Copyright (c) 1998 National Semiconductor Corporation.
 * All Rights Reserved.
 *
 * This software is the confidential and proprietary information of National 
 * Semiconductor Corporation. ("Confidential Information").
 * You shall not disclose such Confidential Information and shall use it only
 * in accordance with the terms of the license agreement you entered into
 * with National Semiconductor Corporation.
 * This code is supplied as is.
 *
 */

/*
 *$Log: /CE/Platform/Nsc/Drivers/Video/gxvideo/ddraw/cognac.h $
 * 
 * 2     4/07/00 9:10a Sarma
 * Removed Cyrix Corporation from the legal/confidentail information. Also
 * added for files not containing this info.
 * 
 *$History: cognac.h $
 * 
 * *****************  Version 2  *****************
 * User: Sarma        Date: 4/07/00    Time: 9:10a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/ddraw
 * Removed Cyrix Corporation from the legal/confidentail information. Also
 * added for files not containing this info.
 *
*/

#ifdef DD_SUPPORT

/* Cognac video register definitions */
#define VC_VID_CFG              0x10000     /* video config */
#define VC_DISP_CFG_BUS         0x10004     /* display config bus */
#define VC_VID_X_POS            0x10008     /* video destination X */
#define VC_VID_Y_POS            0x1000C     /* video destination Y */
#define VC_VID_SCALE            0x10010     /* video scale factor */
#define VC_COLOR_KEY            0x10014     /* video color key */
#define VC_COLOR_MASK           0x10018     /* video color key mask */
#define VC_PAL_HOST_ADDR        0x1001C     /* palette host address */
#define VC_PAL_READ_DATA        0x10020     /* palette read data */
#define VC_DOT_CLK_CONFIG       0x10024
#define VC_CRCSIG_TFT_TV        0x10028


/* Dhruva specific registers */

#define VC_VID_DHRUVA_BYPASS    0x10100    /* Register to Enable Dhruva Bypass */


/*  VC_VID_CFG bits */

#define VC_VCFG_ENABLE          0x00000001      /* video enable */
#define VC_VCFG_REG_UPDATE      0x00000002      /* video register update */
#define VC_VCFG_VID_FMT         0x0000000C      /* video input format  */
                                                /*     LSB         MSB */
                                                /* 0 = U   Y0  V   Y1  */
                                                /* 1 = Y1  V   Y0  U   */
                                                /* 2 = Y0  U   Y1  V   */
                                                /* 3 = Y0  V   Y1  U   */
#define VC_VF_UY0VY1              0
#define VC_VF_Y1VY0U              1
#define VC_VF_Y0UY1V              2
#define VC_VF_Y0VY1U              3

#define VC_VCFG_GV_SCALE_SEL    0x00000010      /* graphics/video scaler input select */
                                                /* 1 = graphics, 0 = video */
#define VC_VCFG_CSC_BYPASS      0x00000020      /* colorspace converter bypass */
#define VC_VCFG_X_FILTER_ON     0x00000040      /* X filter enable */
#define VC_VCFG_Y_FILTER_ON     0x00000080      /* Y filter enable */
#define VC_VCFG_LINE_SIZE       0x0000FF00      /* video source line size in DWORDs */
#define VC_VCFG_INIT_RD_ADDR    0x00FF0000      /* video source clip offset in DWORDs */
#define VC_VCFG_MPEG2_ON        0x01000000      /* MPEG2 enable Cx5520 */
#define VC_VCFG_INIT_RD_MSB     0x01000000      /* Initial buffer read address MSB Cx5530 */
#define VC_VCFG_EARLY_RDY       0x02000000      /* Early video ready */
#define VC_VCFG_LINE_SIZE_MSB   0x08000000      /* Line size MSB */
#define VC_VCFG_420_MODE        0x10000000      /* 4:2:0 YUV mode */
#define VC_VCFG_16BIT_VI        0x20000000      /* 16 bit video interface */
#define VC_VCFG_HIGH_SPEED      0x40000000      /* High speed timings */

/*  VC_DISP_CFG_BUS bits */

#define VC_DCFGB_DISP_CFG       0x07FFFFFF      /* display config [26:0] */
#define VC_DCFGB_FP_ON          0x08000000      /* FP on */
#define VC_DCFGB_CMP_BLUE       0x10000000      /* compare blue */
#define VC_DCFGB_CMP_GREEN      0x20000000      /* compare green */   
#define VC_DCFGB_CMP_RED        0x40000000      /* compare red */   
#define VC_DCFGB_CMP_DDC_SDA    0x80000000      /* DDC SDA */   
           
/*  VC_DISP_CFG bits */                        
                                               
#define VC_DCFG_DSPE            0x00000001      /* display enable */
#define VC_DCFG_HSYE            0x00000002      /* CRT horizontal sync enable */
#define VC_DCFG_VSYE            0x00000004      /* CRT vertical sync enable */
#define VC_DCFG_BLKE            0x00000008      /* DAC blank enable */
#define VC_DCFG_DDC_CLK         0x00000010      /* DDC clock out */
#define VC_DCFG_DAC_PD          0x00000020      /* DAC power down */
#define VC_DCFG_FPPE            0x00000040      /* FP power enable */
#define VC_DCFG_FPDE            0x00000080      /* FP data enable */
#define VC_DCFG_CHSP            0x00000100      /* CRT horizontal sync polarity */
#define VC_DCFG_CVSP            0x00000200      /* CRT vertical sync  polarity */
#define VC_DCFG_FHSP            0x00000400      /* FP horizontal sync polarity */
#define VC_DCFG_FVSP            0x00000800      /* FP vertical sync  polarity */
#define VC_DCFG_FXGA            0x00001000      /* XGA FP */
#define VC_DCFG_DITE            0x00002000      /* FP dither enable */
#define VC_DCFG_SSKW            0x0001C000      /* CRT sync skew */
#define VC_DCFG_PDLY            0x000E0000      /* Power sequence delay */
#define VC_DCFG_VGCK            0x00100000      /* color key input select */
                                                /* 1 = video, 0 = graphics */
#define VC_DCFG_GVPB            0x00200000      /* palette bypass */
                                                /* 1 = graphics, 0 = video */

/*  VC_VID_X/Y_POS bits */

#define VC_POS_X_START          0x000007FF      /* video x start */
#define VC_POS_X_END            0x07FF0000      /* video x end */
#define VC_POS_Y_START          0x000007FF      /* video y start */
#define VC_POS_Y_END            0x07FF0000      /* video y end */
#define VC_SCALE_X              0x00003FFF      /* video x scale */
#define VC_SCALE_Y              0x3FFF0000      /* video y scale */
                                                /* scale = 8K * (Xs - 1) / (Xd - 1)

/* FourCC codes supported */

#define FOURCC_YUY2   0x32595559
#define FOURCC_YVYU   0x55595659
#define FOURCC_UYVY   0x59565955
#define FOURCC_EMMA   0x99999999
#define FOURCC_YUYV   0x56595559

/* END OF FILE */
#endif //DD_SUPPORT